AD9789BBCZ datasheet(58/76 Pages) AD

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AD9789

Rev. A | Page 58 of 76

Optimizing the Clock Common-Mode Voltage

In addition to the system that optimizes the handoff timing, an

additional system sets the common-mode voltage of the clock.

This system can be used to properly align the crossing point of

the CLKP and CLKN signals to ensure that the duty cycle of the

clock is set properly. Figure 115 shows how the common-mode

voltage of CLKP and CLKN is set. There are eight switches

controlled by the CLKP_CML bits (Register 0x32[4:1]) and the

CLKN_CML bits (Register 0x31[7:4]) for both the CLKP and

CLKN signals. The direction of the adjustment is determined by

the PSIGN and NSIGN bits (Register 0x32, Bit 5 and Bit 0). If

PSIGN and NSIGN are low, the common-mode voltage decreases

with CLKP_CML/CLKN_CML values. If PSIGN and NSIGN are

high, the common-mode voltage increases with CLKP_CML/

CLKN_CML values, as shown in Figure 116. With both

CLKP_CML and CLKN_CML set to 0, the feedback path forces

the common-mode voltage to be set to approximately 0.9 V. The

optimal ac performance occurs at a setting of −15 on both the

CLKP and CLKN offset bits.

CLKP/CLKN

CVDD18

CLKx_CML

SIGN = 0

CLKx_CML

SIGN = 1

Figure 115. Clock Common-Mode Control

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

–15 –13 –11 –9 –7 –5 –3 –1

9 11 13 15

OFFSET CODE

CLKP

CLKN

Figure 116. Common-Mode Voltage with Respect to CLKP_CML/CLKN_CML

and PSIGN/NSIGN

Clock Phase Noise Effects on AC Performance

The quality of the clock source driving the ADCLK914 deter-

mines the achievable ACLR performance of the AD9789.

Table 76 summarizes the close-in ACLR for a four-carrier

DOCSIS signal at 900 MHz with respect to various phase

noise profiles. (All ACLR values are specified in dBc.)

Table 76. Four-Carrier DOCSIS Close-In ACLR Performance

at 900 MHz for Various Phase Noise Profiles

Phase Noise (dBc)

Band

Profile 1

Profile 2

Profile 3

Profile 4

Spec

750 kHz

to 6 MHz

−71

−67.2

−62.4

−59.1

−60

6 MHz to

12 MHz

−70.9

−70.3

−67

−63.8

−63

12 MHz to

18 MHz

−71

−70.8

−65

Table 77 shows the phase noise at various offsets for each

profile. (All phase noise numbers are specified in dBc/Hz.)

Table 77. Phase Noise Summary for Each Profile

Phase Noise (dBc/Hz)

Offset1

Profile 1

Profile 2

Profile 3

Profile 4

2 kHz

−114.8

−112.8

−111.7

−111.2

20 kHz

−117.8

−115.5

−114.6

−113.8

200 kHz

−128.3

−118.9

−118.3

−116.8

2 MHz

−148.5

−127.9

−122.2

−117.9

20 MHz

−152.5

−149.9

−148

−145.7

1 At offsets less than 500 kHz, the measurement instrument dominates the

phase noise performance.

To meet the close-in ACLR requirements for four-carrier

DOCSIS, the phase noise found in Profile 3 is the minimum

requirement necessary.

MU DELAY CONTROLLER

The mu delay adjusts timing between the digital and analog

blocks. The mu delay controller receives phase relational

information between the digital and analog clock domains. The

control system continuously adjusts the mu delay to maintain

the desired phase relationship between the digital and analog

sections. A top level diagram of the mu delay within the DAC is

shown in Figure 117.

14-BIT

2.4GSPS

DAC

DIGITAL

CIRCUITRY

MU Φ

CONTROL

Φ DET

DELAY

16-BIT

DATA

DAC

CLOCK

Figure 117. Mu Delay Controller Block Diagram

The mu controller has two modes of operation: initial phase

search and phase tracking. In the phase search mode, the con-

troller looks for the initial mu delay value to use before going

into tracking mode. In tracking mode, the controller makes

adjustments to the initial mu delay value to keep the phase at

the desired value. The initial phase search is required because

multiple mu delay settings may result in the desired phase, but

the device may not operate correctly at all of those mu delay values.

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