AD9789BBCZ datasheet(2/76 Pages) AD

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AD9789

Rev. A | Page 2 of 76

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Detailed Functional Block Diagrams............................................. 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Digital Specifications ................................................................... 5

AC Specifications.......................................................................... 6

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 22

Serial Control Port.......................................................................... 23

Serial Control Port Pin Descriptions ....................................... 23

General Operation of Serial Control Port............................... 23

Instruction Word (16 Bits) ........................................................ 24

MSB/LSB First Transfers............................................................ 24

SPI Register Map............................................................................. 27

SPI Register Descriptions.......................................................... 29

Theory of Operation ...................................................................... 39

Datapath Signal Processing....................................................... 39

Digital Block Upconverter ........................................................ 43

Digital Interface Modes ............................................................. 45

Analog Modes of Operation ..................................................... 54

Analog Control Registers .......................................................... 55

Voltage Reference ....................................................................... 56

DAC Output Stages .................................................................... 56

Clocking the AD9789 ................................................................ 57

Mu Delay Controller.................................................................. 58

Interrupt Requests...................................................................... 61

Recommended Start-Up Sequence .......................................... 62

Customer BIST Modes................................................................... 63

Using the Internal PRN Generator to Test QAM Output AC

Performance ................................................................................ 63

Using the Internal Built-In Self-Test (BIST) to Test for Digital

Data Input Connectivity............................................................. 63

QAM Constellation Maps ............................................................. 65

Channelizer Mode Pin Mapping for CMOS and LVDS............ 68

Outline Dimensions ....................................................................... 74

Ordering Guide .......................................................................... 74

REVISION HISTORY

7/11—Rev. 0 to Rev. A

Changes to Table 2, DAC Clock Input (CLKP, CLKN): Added

DAC Clock Rate Parameter............................................................. 5

Changes to Table 3, Dynamic Performance, DAC Update Rate

Parameter; Added Adjusted DAC Update Rate Parameter......... 6

Changes to Captions for Figure 42, Figure 44, Figure 46,

Figure 49 .......................................................................................... 18

Changes to Digital 16x Tunable Band-Pass Filter Section, Third

Paragraph......................................................................................... 44

Changes to Retimer and Latency Look-Up Tables Section,

Second Paragraph ........................................................................... 50

Changes to Captions for Figure 122, Figure 124, Figure 125.... 65

4/09—Revision 0: Initial Version

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