ADS5277IPFP datasheet(24/32 Pages) TI

24 / 32 page

RESET

POWER-DOWN MODE

LAYOUT OF PCB WITH PowerPAD

CONNECTING HIGH-SPEED,

ADS5277

SBAS333D – FEBRUARY 2005 – REVISED JANUARY 2009............................................................................................................................................ www.ti.com

It is recommended that the isolation be maintained

onboard by using separate supplies to drive AVDD

After the supplies have stabilized, it is required to

and LVDD, as well as separate ground planes for

give the device an active RESET pulse. This results

AVSS and LVSS.

in all internal registers resetting to their default value

The use of LVDS buffers reduces the injected noise

of 0 (inactive). Without a reset, it is possible that

considerably, compared to CMOS buffers. Also, the

some registers may be in their non-default state on

low output swing, as well as the differential nature of

power-up. This may cause the device to malfunction.

the LVDS buffer, results in low-noise coupling.

When a reset is active, the device outputs ‘0’ code on

all channels. However, the LVDS output clocks are

unaffected by reset.

The ADS5277 has a power-down pin, referred to as

PD. Pulling PD high causes the device to enter the

THERMALLY-ENHANCED PACKAGES

power-down mode. In this mode, the reference and

clock circuitry as well as all the channels are powered

The ADS5277 is housed in an 80-lead PowerPAD

down and device power consumption drops to less

thermally-enhanced package. To make optimum use

than 100mW. In power-down mode, the internal

the

thermal

efficiencies

designed

into

the

buffers driving REFT and REFB are tri-stated and their

PowerPAD package, the printed circuit board (PCB)

outputs are forced to a voltage roughly equal to half

must be designed with this technology in mind.

of the voltage on AVDD. Speed of recovery from

Please

refer

PowerPAD

brief

SLMA004,

power-down mode depends on the value of the

PowerPAD Made Easy (available for download at

external capacitance on the REFT and REFB pins. For

www.ti.com),

which

addresses

the

specific

capacitances on REFT and REFB less than 1µF, the

considerations

required

when

integrating

reference voltages settle to within 1% of their steady

PowerPAD package into a PCB design. For more

state values in less than 500

µs. Individual channels

detailed information, including thermal modeling and

can

also

selectively

powered

down

repair

procedures,

please

see

technical

brief

programming registers.

SLMA002, PowerPAD Thermally-Enhanced Package

(www.ti.com).

The ADS5277 also has an internal circuit that

monitors the state of stopped clocks. If ADCLK is

Interfacing High-Speed LVDS Outputs (SBOA104),

stopped for longer than 300ns (or if it runs at a speed

an application report discussing the design of a

less than 3MHz), this monitoring circuit generates a

simple deserializer that can deserialize LVDS outputs

logic signal

that

puts

the

device

partial

up to 840Mbps, can also be found on the TI web site

power-down

state.

result,

the

power

(www.ti.com).

consumption of the device is reduced when ADCLK is

stopped.

The

recovery

from

such

partial

power-down takes

approximately

100

µs; this is

MULTI-CHANNEL ADCs TO XILINX FPGAs

described in Table 2.

A separate application note (XAPP774) describing

how to connect TI's high-speed, multi-channel ADCs

with serial LVDS outputs to Xilinx FPGAs can be

downloaded

directly

from

the

Xilinx

web

site

(http://www.xilinx.com).

Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage

DESCRIPTION

TYP

REMARKS

Recovery from power-down mode (PD = 1 to PD = 0).

500

µs

Capacitors on REFT and REFB less than 1µF.

Recovery from momentary clock stoppage ( < 300ns).

µs

Recovery from extended clock stoppage ( > 300ns).

100

µs

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