AD5306 datasheet(17/24 Pages) AD

17 / 24 page

AD5306/AD5316/AD5326

Rev. F | Page 17 of 24

DEFAULT READBACK CONDITIONS

All pointer byte bits power up to 0. Therefore, if the user

initiates a readback without first writing to the pointer byte, no

single DAC channel has been specified. In this case, the default

readback bits are all 0 except for the CLR bit and the PD bit,

which are 1.

MULTIPLE DAC WRITE SEQUENCE

Because there are individual bits in the pointer byte for each DAC,

it is possible to write the same data and control bits to two, three,

or four DACs simultaneously by setting the relevant bits to 1.

MULTIPLE DAC READBACK SEQUENCE

If the user attempts to read back data from more than one DAC

at a time, the part reads back the power-on condition of GAIN,

BUF, and data bits (all 0), and the current state of CLR and PD.

BUF

CLR

GAIN

LSB

MSB

8-BIT AD5306

CLR

D11

D10

MOST SIGNIFICANT DATA BYTE

LSB

MSB

10-BIT AD5316

LSB

MSB

12-BIT AD5326

CLR

LEAST SIGNIFICANT DATA BYTE

LSB

MSB

8-BIT AD5306

LSB

MSB

10-BIT AD5316

LSB

MSB

12-BIT AD5326

BUF

GAIN

BUF

GAIN

Figure 32. Data Formats for Write and Readback

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