DRV201A ADDRESS

0

0

0

1

1

1

0

1

DATA

CURRENT REGISTER NUMBER K

REGISTER NUMBER K+1

K+2

DATA

DATA

L bytes of DATA

REGISTER NUMBER K+L-1

K+L

DRV201A ADDRESS

0

0

0

1

1

1

0

0

REGISTER NUMBER

M

DATA

CURRENT REGISTER NUMBER K

REGISTER NUMBER M

DATA

REGISTER NUMBER M+1

M+2

DATA

REGISTER NUMBER M+L-1

M+L

L bytes of DATA

DRV201A ADDRESS

0

0

0

1

1

1

0

1

DATA

REGISTER NUMBER M

REGISTER NUMBER M+1

K+2

DATA

DATA

L bytes of DATA

REGISTER NUMBER M+L-1

M+L

DRV201A ADDRESS

0

0

0

1

1

1

0

0

REGISTER NUMBER

M

CURRENT REGISTER NUMBER K

0

0

0

1

1

1

0

1

DATA

0

0

0

1

1

1

0

1

DATA

CURRENT REGISTER NUMBER K

REGISTER NUMBER K+1

K+2

DRV201A ADDRESS

DRV201A ADDRESS

DRV201A

SLVSBN6 – JUNE 2013

www.ti.com

Figure 9. Single Read from the Current Location

Sequential Read and Write

Sequential read and write allows simple and fast access to DRV201A registers. Figure 10 shows sequential read

from a defined location. If the master doesn’t issue a stop condition after giving ACK, DRV201A auto increments

the register number and writes the data from the next register.

Figure 10. Sequential Read from a Defined Location

Figure 11 shows the sequential write. If the master doesn’t issue a stop condition after giving ACK, DRV201A

auto increments it’s register by one and the master can write to the next register.

Figure 11. Sequential Write

If read is started without writing the register value first, DRV201A writes out data from the current location. If the

the data. This continues until the master issues a stop condition. This is shown in Figure 12.

Figure 12. Sequential Read Starting from a Current Location

I

Data transmission is initiated with a start bit from the controller as shown in Figure 13. The start condition is

recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon

reception of a start bit, the device will receive serial data on the SDA input and check for valid address and

control information. SDA data is latched by DRV201A on the rising edge of the SCL line. If the appropriate device

address bits are set for the device, DRV201A issues the ACK by pulling the SDA line low on the next falling edge

after 8th bit is latched. SDA is kept low until the next falling edge of the SCL line.

14

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