MPC9772 datasheet(8/17 Pages) IDT

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MPC9772 REVISION 7 JANUARY 8, 2013

MPC9772 Data Sheet

3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

APPLICATIONS INFORMATION

MPC9772 Configurations

Configuring the MPC9772 amounts to properly configuring

the internal dividers to produce the desired output

frequencies. The output frequency can be represented by

this formula:

where fREF is the reference frequency of the selected input

clock source (CCLKO, CCLK1 or XTAL interface), M is the

PLL feedback divider and N is a output divider. The PLL

feedback divider is configured by the FSEL_FB[2:0] and the

output dividers are individually configured for each output

bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0]

inputs.

The reference frequency fREF and the selection of the

feedback-divider M is limited by the specified VCO frequency

range. fREF and M must be configured to match the VCO

frequency range of 200 to 480 MHz in order to achieve stable

PLL operation:

fVCO,MIN  (fREF  VCO_SEL  M)  fVCO,MAX

The PLL post-divider VCO_SEL is either a divide-by-one

or a divide-by-two and can be used to situate the VCO into

the specified frequency range. This divider is controlled by

the VCO_SEL pin. VCO_SEL effectively extends the usable

input frequency range while it has no effect on the output to

reference frequency ratio.

The output frequency for each bank can be derived from

the VCO frequency and output divider:

fQA[0:3] = fVCO  (VCO_SEL  NA)

fQB[0:3] = fVCO  (VCO_SEL  NB)

fQC[0:3] = fVCO  (VCO_SEL  NC)

Table 11 shows the various PLL feedback and output

dividers and Figure 3 and Figure 4 display example

configurations for the MPC9772:

VCO_SEL

M

N

fREF

fOUT

fOUT = fREF  M  N

PLL

Table 11. MPC9772 Divider

Divider

Function

VCO_SEL

Values

PLL feedback

FSEL_FB[0:3]

1

4, 6, 8, 10, 12, 16

2

8, 12, 16, 20, 24, 32, 40

Bank A Output

Divider

FSEL_A[0:1]

1

4, 6, 8, 12

2

8, 12, 16, 24

Bank B Output

Divider

FSEL_B[0:1]

1

4, 6, 8, 10

2

8, 12, 16, 20

Bank C Output

Divider

FSEL_C[0:1]

1

2, 4, 6, 8

2

4, 8, 12, 16

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