MPC9772 REVISION 7 JANUARY 8, 2013

12

©2013 Integrated Device Technology, Inc.

MPC9772 Data Sheet

3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

(CF) can be derived from Table 12.

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device.

Due to the frequency dependence of the static phase

offset and I/O jitter, using Figure 9 to Figure 11 to predict a

the input reference frequency results in a precise timing

performance analysis.

In the following example calculation an I/O jitter confidence

factor of 99.7% (

 3) is assumed, resulting in a worst case

timing uncertainty from the common input reference clock to

any output of –455 ps to +455 ps relative to CCLK (PLL

feedback =

8, reference frequency = 50 MHz, VCO

frequency = 400 MHz, I/O jitter = 13 ps rms max., static

Figure 9. MPC9772 I/O Jitter

Figure 10. MPC9772 I/O Jitter

Figure 11. MPC9772 I/O Jitter

Driving Transmission Lines

The MPC9772 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

 the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Freescale Semiconductor

application note AN1091. In most high performance clock

networks point-to-point distribution of signals is the method of

choice. In a point-to-point scheme either series terminated or

parallel terminated transmission lines can be used. The

parallel technique terminates the signal at the end of the line

with a 50

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9772 clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 12

illustrates an output driving a single series terminated line

versus two series terminated lines in parallel. When taken to

its extreme the fanout of the MPC9772 clock driver is

effectively doubled due to its capability to drive multiple lines.

Table 12. Confidence Factor CF

CF

Probability of Clock Edge

within the Distribution

 1

0.68268948

 2

0.95449988

 3

0.99730007

 4

0.99993663

 5

0.99999943

 6

0.99999999

VCO Frequency [MHz]

200

250

300

350

400

450

480

160

140

120

100

80

60

40

20

0

FB=

32

FB=

16

FB=

8

FB=

4

Max. I/O Phase Jitter versus Frequency

Parameter: PLL Feedback Divider FB

VCO Frequency [MHz]

200

250

300

350

400

450

480

120

100

80

60

40

20

0

FB=

12

FB=

24

Max. I/O Phase Jitter versus Frequency

Parameter: PLL Feedback Divider FB

FB=

6

VCO Frequency [MHz]

200

250

300

350

400

450

480

140

120

100

80

60

40

20

0

FB=

20

FB=

10

FB=

40

Max. I/O Phase Jitter versus Frequency

Parameter: PLL Feedback Divider FB