GL3233 Product Overview

©2012 Genesys Logic, Inc. - All rights reserved.

Page 5

BLOCK DIAGRAM

Functional Block Diagram

Super Speed and HS/FS PHY

The transceiver macro is the analog circuitry that handles the low level USB protocol and signaling, and shifts

the clock domain of the data from the USB to one that is compatible with the general logic.

USB Controller

The USB Controller, which contains the USB PID and address recognition logic, and other sequencing and

state machine logic to handle USB packets and transactions.

EPFIFO

Endpoint FIFO includes Control FIFO (FIFO0) and Bulk In/Out FIFO

EP0 FIFO

FIFO of control endpoint 0. It is 512-byte FIFO and used for endpoint 0 data transfer.

Bulk In/Out FIFO It can be in the TX mode or RX mode:

1. It can be transmit/receive 512-byte data of USB 2.0 and 1K-byte data of USB 3.0

continuously.

2. It can be directly accessed by micro-controller

MCU

8051 micro-controller inside.

8051 Core

Compliant with Intel 8051 high speed micro-controller

ROM

Firmware code on ROM

SRAM

Internal RAM area for MCU access