L9952GXPTR datasheet(18/68 Pages) STMICROELECTRONICS

18 / 68 page

Description

L9952GXP

18/68

Doc ID 13518 Rev 5

The watchdog is triggered by toggling the trigger bit (CR0, D19).

Note:

The active trigger window will be reset after each correct trigger write operation.

In case of reset (NReset low for 2ms) the trigger bit is set to “0”.

In case of a WD failure, the outputs (Lsx, Hsx, V2) are switched off and NReset is pulled low

for 2ms.

Writing to control register 0 without inverting the WD trigger bit is possible at any time.

Figure 4.

Watchdog

Watchdog active

With

Normal window

(10ms)

HSD, LSD : according to

CR0

Reset

(Nreset =low for 2ms)

LSD: Off (control bits set to ‚0')

HSD: Off (control bits remain

unchanged)

Watchdog active

with

‚long open window’

(65ms nom)

HS and LS outputs are

off

Watchdog

Inactive

(standby modes,

Flash Mode)

Watchdog Failure (‚long

open window’ passed

without TRIG=1

2ms

Set WD Trigger Bit = ‚1' or

toggle trigger bit if wake-up

from V1standby

Set

WD Trigger Bit = ‚0' or write

non-inverting value to trigger

bit after wake-up from

V1standby mode

Go to standby mode or

Flash Mode (PWM2>9V)

Go to standby mode

or Flash Mode (PWM2>9V)

Power-on

Reset

Toggle WD Trigger Bit

Within nominal window

Wake-up event

or exit Flash Mode

V1 off

for 200 ms

8x WD Failure

Watchdog Failure

Vbatstdby

Mode

8+7

WD Failures

Wake up event

t=200ms

INH, LIN, SPI

I(V1)>1mA and ICMP=0

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