AD7685

Rev. C | Page 6 of 28

−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 5. VDD = 2.3V to 4.5 V1

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

0.7

3.2

μs

Acquisition Time

1.8

μs

Time Between Conversions

5

μs

CNV Pulse Width (CS Mode)

10

ns

SCK Period (CS Mode)

25

ns

SCK Period (Chain Mode)

VIO Above 3 V

29

ns

VIO Above 2.7 V

35

ns

VIO Above 2.3 V

40

ns

SCK Low Time

12

ns

SCK High Time

12

ns

SCK Falling Edge to Data Remains Valid

5

ns

SCK Falling Edge to Data Valid Delay

VIO Above 3 V

24

ns

VIO Above 2.7 V

30

ns

VIO Above 2.3 V

35

ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 2.7 V

18

ns

VIO Above 2.3 V

22

ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

25

ns

SDI Valid Setup Time from CNV Rising Edge (CS Mode)

30

ns

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

0

ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

5

ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

8

ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

5

ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

4

ns

SDI High to SDO High (Chain Mode with Busy Indicator)

36

ns

500µA

500µA

1.4V

TO SDO

50pF

Figure 3. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

NOTES

1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 4. Voltage Levels for Timing