M68HC08 datasheet(217/332 Pages) FREESCALE

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Serial Communications Interface Module (SCI)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

Serial Communications Interface Module (SCI)

217

NOTE:

When queueing an idle character, return the TE bit to logic 1 before the

stop bit of the current character shifts out to the TxD pin. Setting TE after

the stop bit appears on TxD causes data previously written to the SCDR

to be lost.

Toggle the TE bit for a queued idle character when the SCTE bit

becomes set and just before writing the next byte to the SCDR.

12.5.2.5 Inversion of Transmitted Output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)

reverses the polarity of transmitted data. All transmitted values, including

idle, break, start, and stop bits, are inverted when TXINV is at logic 1.

(See 12.9.1 SCI Control Register 1.)

12.5.2.6 Transmitter Interrupts

These conditions can generate CPU interrupt requests from the SCI

transmitter:

•

SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates

that the SCDR has transferred a character to the transmit shift

Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2

enables the SCTE bit to generate transmitter CPU interrupt

requests.

•

Transmission complete (TC) — The TC bit in SCS1 indicates that

the transmit shift register and the SCDR are empty and that no

break or idle character has been generated. The transmission

complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to

generate transmitter CPU interrupt requests.

M68HC08 Datasheet(PDF) 217 Page - Freescale Semiconductor, Inc