M68HC08 datasheet(160/332 Pages) FREESCALE

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Timer Interface Module (TIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

160

Timer Interface Module (TIM)

Freescale Semiconductor

In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the

TIM channel x registers (TCHxH) inhibits input captures until the low

byte (TCHxL) is read.

In output compare mode (MSxB:MSxA

≠ 0:0), writing to the high byte of

the TIM channel x registers (TCHxH) inhibits output compares until the

low byte (TCHxL) is written.

Address: T1CH0H, $0011 and T2CH0H, $0047

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

Figure 10-12. TIM Channel 0 Register High (TCH0H)

Address: T1CH0L, $0012 and T2CH0L $0048

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

Indeterminate after reset

Figure 10-13. TIM Channel 0 Register Low (TCH0L)

Address: T1CH1H, $0014 and T2CH1H, $004A

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

Figure 10-14. TIM Channel 1 Register High (TCH1H)

Address: T1CH1L, $0015 and T2CH1L, $004B

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

Indeterminate after reset

Figure 10-15. TIM Channel 1 Register Low (TCH1L)

M68HC08 Datasheet(PDF) 160 Page - Freescale Semiconductor, Inc

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