M68HC08 datasheet(156/332 Pages) FREESCALE

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Timer Interface Module (TIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

156

Timer Interface Module (TIM)

Freescale Semiconductor

10.10.4 TIM Channel Status and Control Registers

Each of the TIM channel status and control registers:

•

Flags input captures and output compares

•

Enables input capture and output compare interrupts

•

Selects input capture, output compare, or PWM operation

•

Selects high, low, or toggling output on output compare

•

Selects rising edge, falling edge, or any edge as the active input

capture trigger

•

Selects output toggling on TIM overflow

•

Selects 0% and 100% PWM duty cycle

•

Selects buffered or unbuffered output compare/PWM operation

CHxF — Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set

when an active edge occurs on the channel x pin. When channel x is

an output compare channel, CHxF is set when the value in the TIM

counter registers matches the value in the TIM channel x registers.

Address: T1SC0, $0010 and T2SC0, $0046

Bit 7

654321

Bit 0

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

00000000

Figure 10-9. TIM Channel 0 Status and Control Register (TSC0)

Address: T1SC1, $0013 and T2SC1, $0049

Bit 7

654321

Bit 0

Read:

CH1F

CH1IE

CH01IE

MS1A

ELS1B

ELS1A

TOV1

CH1MAX

Write:

Reset:

00000000

Figure 10-10. TIM Channel 1 Status and Control Register (TSC1)

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