M68HC08 datasheet(154/332 Pages) FREESCALE

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Timer Interface Module (TIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

154

Timer Interface Module (TIM)

Freescale Semiconductor

PS[2:0] — Prescaler Select Bits

These read/write bits select one of the seven prescaler outputs as the

input to the TIM counter as Table 10-2 shows. Reset clears the

PS[2:0] bits.

10.10.2 TIM Counter Registers

The two read-only TIM counter registers contain the high and low bytes

of the value in the TIM counter. Reading the high byte (TCNTH) latches

the contents of the low byte (TCNTL) into a buffer. Subsequent reads of

TCNTH do not affect the latched TCNTL value until TCNTL is read.

Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)

also clears the TIM counter registers.

NOTE:

If you read TCNTH during a break interrupt, be sure to unlatch TCNTL

by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL

retains the value latched during the break.

Table 10-2. Prescaler Selection

PS2

PS1

PS0

TIM Clock Source

Internal bus clock

÷ 1

Internal bus clock

÷ 2

Internal bus clock

÷ 4

Internal bus clock

÷ 8

Internal bus clock

÷ 16

Internal bus clock

÷ 32

Internal bus clock

÷ 64

111

TCLK

Address: T1CNTH, $000C and T2CNTH, $0042

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

00000000

= Unimplemented

Figure 10-5. TIM Counter Registers High (TCNTH)

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