M68HC08 datasheet(151/332 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

Timer Interface Module (TIM)

151

10.9 I/O Signals

Port E shares three of its pins with the TIM. PTE0/TCLK is an external

clock input to the TIM prescaler. The two TIM channel I/O pins are

PTE1/T1CH01 and PTE2/T2CH01.

10.9.1 TIM Clock Pin (PTE0/TCLK)

PTE0/TCLK is an external clock input that can be the clock source for

the TIM counter instead of the prescaled internal bus clock. Select the

PTE0/TCLK input by writing logic 1s to the three prescaler select bits,

PS[2:0]. (See 10.10.1 TIM Status and Control Register.) The minimum

TCLK pulse width, TCLK

LMIN or TCLKHMIN, is:

The maximum TCLK frequency is:

bus frequency

÷ 2

PTE0/TCLK is available as a general-purpose I/O pin when not used as

the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it

is an input regardless of the state of the DDRE0 bit in data direction

10.9.2 TIM Channel I/O Pins (PTE1/T1CH01:PTE2/T2CH01)

Each TIM I/O pin is programmable independently as an input capture pin

or an output compare pin, or configured as buffered output compare or

buffered PWM pins.

bus frequency

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M68HC08 Datasheet(PDF) 151 Page - Freescale Semiconductor, Inc