M68HC08 datasheet(150/332 Pages) FREESCALE

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Timer Interface Module (TIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

150

Timer Interface Module (TIM)

Freescale Semiconductor

10.7.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait

mode, the TIM registers are not accessible by the CPU. Any enabled

CPU interrupt request from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power

consumption by stopping the TIM before executing the WAIT instruction.

10.7.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP

instruction does not affect register conditions or the state of the TIM

counter. TIM operation resumes when the MCU exits stop mode after an

external interrupt.

10.8 TIM During Break Interrupts

A break interrupt stops the TIM counter.

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM break flag control register (SBFCR) enables software to clear

status bits during the break state. (See 8.8.3 SIM Break Flag Control

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

I/O registers during the break state without affecting status bits. Some

status bits have a 2-step read/write clearing procedure. If software does

the first step on such a bit before the break, the bit cannot change during

the break state as long as BCFE is at logic 0. After the break, doing the

second step clears the status bit.

M68HC08 Datasheet(PDF) 150 Page - Freescale Semiconductor, Inc