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IMX53IEC Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc |
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IMX53IEC Datasheet(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 173 page ![]() Electrical Characteristics i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 61 4.6.7 DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2, and DDR3) The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008, supporting DDR2-800 and LVDDR2-800. The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting DDR3-800. The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800. WE43 Input Data Valid to CSx_B Invalid MAXCO - MAXCSO + MAXDI MAXCO - MAXCSO + MAXDI —ns WE44 CSx_B Invalid to Input Data invalid 00 — ns WE45 CSx_B Valid to BEy_B Valid (Write access) WE12 - WE6 + (WBEA - CSA) — 3 + (WBEA - CSA) ns WE46 BEy_B Invalid to CSx_B Invalid (Write access) WE7 - WE13 + (WBEN - CSN) — -3 + (WBEN - CSN) ns MAXDTI DTACK MAXIMUM delay from chip dtack input to its internal FF + 2 cycles for synchronization —— — WE47 Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI MAXCO - MAXCSO + MAXDTI —ns WE48 CSx_B Invalid to Dtack invalid 0 0 — ns 1 Parameters WE4... WE21 value see column BCD = 0 in Table 38. 2 All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units. 3 CS Assertion. This bit field determines when CS signal is asserted during read/write cycles. 4 CS Negation. This bit field determines when CS signal is negated during read/write cycles. 5 t is axi_clk cycle time. 6 BE Assertion. This bit field determines when BE signal is asserted during read cycles. 7 BE Negation. This bit field determines when BE signal is negated during read cycles. Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select Ref No. Parameter Determination by Synchronous measured parameters 12 Min Max (If 133 MHz is supported by SOC) Unit |
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