 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IMX53IEC Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
IMX53IEC Datasheet(HTML) 62 Page - Freescale Semiconductor, Inc |
|
|
62 / 173 page  i.MX53 Applications Processors for Industrial Products, Rev. 6 62 Freescale Semiconductor Electrical Characteristics Figure 28 and Table 40 show the address and control timing parameters for DDR2 and DDR3. Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3 Table 40. DDR SDRAM Timing Parameter Table1 2 1 All timings are refer to Vref level cross point. 2 Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF. ID Parameter Symbol SDCLK = 400 MHz Units Min Max DDR1 SDRAM clock high-level width tCH 0.48 0.52 tCK DDR2 SDRAM clock low-level width tCL 0.48 0.52 tCK DDR4 CS, RAS, CAS, CKE, WE, ODT setup time tIS 0.6 — ns DDR5 CS, RAS, CAS, CKE, WE, ODT hold time tIH 0.6 — ns DDR6 Address output setup time tIS 0.6 — ns DDR7 Address output hold time tIH 0.6 — ns SDCLK WE ADDR ROW/BA COL/BA CS CAS RAS DDR1 DDR2 DDR4 DDR4 DDR4 DDR5 DDR5 DDR5 DDR5 DDR6 DDR7 SDCLK ODT/CKE DDR4 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
