GD82541PI datasheet(7/46 Pages) INTEL

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Networking Silicon — 82541(PI/GI/EI)

1.0

Introduction

The Intel

® 82541(PI/GI/EI) Gigabit Ethernet is a single, compact component with an integrated

Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop,

workstation and mobile PC Network designs with critical space constraints, the Intel

® 82541(PI/

GI/EI) allows for a Gigabit Ethernet implementation in a very small area that is footprint

compatible with current generation 10/100 Mbps Fast Ethernet designs.

The Intel

® 82541(PI/GI/EI) integrates fourth generation gigabit MAC design with fully integrated,

physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable

of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to

managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral

Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz.

The 82541(PI/GI/EI) also incorporates the Clock Run protocol and hardware supported downshift

capability to two-pair and three-pair 100 Mbps operation. These features optimize mobile

applications.

The 82541(PI/GI/EI) on-board System Management Bus (SMB) port enables network

manageability implementations required by information technology personnel for remote control

and alerting via the Local Area Network (LAN). With SMB, management packets can be routed to

or from a management processor. The SMB port enables industry standards, such as Intelligent

Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2.0, to be implemented

using the 82541(PI/GI/EI). In addition, on chip ASF 2.0 circuitry provides alerting and remote

control capabilities with standardized interfaces.

The 82541(PI/GI/EI) Gigabit Ethernet Controller Architecture is designed for high performance

and low memory latency. Wide internal data paths eliminate performance bottlenecks by efficiently

handling large address and data words. The 82541(PI/GI/EI) controller includes advanced interrupt

handling features to limit PCI bus traffic and a PCI interface that maximizes efficient bus usage.

The 82541(PI/GI/EI) uses efficient ring buffer descriptor data structures, with up to 64 packet

descriptors cached on chip. A large 64-KByte onchip packet buffer maintains superior performance

as available PCI bandwidth changes. In addition, using hardware acceleration, the controller

offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP

segmentation.

The 82541(PI/GI/EI) is packaged in a 15 mm x 15 mm 196-ball grid array and is pin compatible

with the 82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller,

82562EZ(EX) Platform LAN Connect devices, and the 82540EP(EM) Gigabit Ethernet Controller.

1.1

Document Scope

The 82541EI is the original device and is now being manufactured in a B0 stepping. The 82541GI

(B1 stepping) and 82541PI (C0 stepping) are pin compatible, however, a different Intel software

driver is required from the 82541EI. This document contains datasheet specifications for the

82541(PI/GI/EI) Gigabit Ethernet Controllers including signal descriptions, DC and AC

parameters, packaging data, and pinout information.

GD82541PI Datasheet(PDF) 7 Page - Intel Corporation

GD82541PI Datasheet(HTML) 7 Page - Intel Corporation

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