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GD82541PI Datasheet(PDF) 28 Page - Intel Corporation |
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GD82541PI Datasheet(HTML) 28 Page - Intel Corporation |
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28 / 46 page  82541(PI/GI/EI) — Networking Silicon 28 NOTES: 1. Output timing measurements are as shown. 2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed. 3. Input timing measurements are as shown. Figure 4. AC Test Loads for General Output Pins Table 18. PCI Bus Interface Timing Parameters Symbol Parameter PCI 66MHz PCI 33 MHz Units MinMax MinMax TVAL CLK to signal valid delay: bussed signals 26 2 11 ns TVAL(ptp) CLK to signal valid delay: point- to-point signals 26 2 12 ns TON Float to active delay 2 2 ns TOFF Active to float delay 14 28 ns TSU Input setup time to CLK: bussed signals 37 ns TSU(ptp) Input setup time to CLK: point-to- point signals 5 10, 12 ns TH Input hold time from CLK 0 0 ns 0.6 Vcc 0.2 Vcc 0.5 Vcc 0.4 Vcc 0.3 Vcc Tcyc Th Tl 0.4 Vcc p-to-p (minimum) 3.3 V Clock |
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