ADC101S021 datasheet(6/23 Pages) TI

6 / 23 page

IOL

200 PA

IOH

200 PA

1.6 V

To Output Pin

25 pF

ADC101S021

SNAS307F – JULY 2005 – REVISED MARCH 2013

www.ti.com

ADC101S021 Timing Specifications

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 1.0 MHz to 4.0 MHz, CL = 25 pF, fSAMPLE = 50

ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol

Parameter

Conditions

Typical

Limits

Units

tCS

Minimum CS Pulse Width

ns (min)

tSU

CS to SCLK Setup Time

ns (min)

tEN

Delay from CS Until SDATA TRI-STATE Disabled (1)

ns (max)

VA = +2.7V to +3.6V

ns (max)

tACC

Data Access Time after SCLK Falling Edge (2)

VA = +4.75V to +5.25V

ns (max)

tCL

SCLK Low Pulse Width

0.4 x tSCLK

ns (min)

tCH

SCLK High Pulse Width

0.4 x tSCLK

ns (min)

VA = +2.7V to +3.6V

ns (min)

SCLK to Data Valid Hold Time

VA = +4.75V to +5.25V

ns (min)

ns (max)

VA = +2.7V to +3.6V

ns (min)

tDIS

SCLK Falling Edge to SDATA High Impedance (3)

ns (max)

VA = +4.75V to +5.25V

ns (min)

tPOWER-

Power-Up Time from Full Power-Down

µs

(1)

Measured with the timing test circuit shown in Figure 2 and defined as the time taken by the output signal to cross 1.0V.

(2)

Measured with the timing test circuit shown in Figure 2 and defined as the time taken by the output signal to cross 1.0V or 2.0V.

(3)

tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 2. The measured number

is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish

time, independent of the bus loading.

Timing Diagrams

Figure 2. Timing Test Circuit

Submit Documentation Feedback

Product Folder Links: ADC101S021

ADC101S021 Datasheet(PDF) 6 Page - Texas Instruments

ADC101S021 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL