IR3823 datasheet(34/41 Pages) IRF

34 / 41 page

IR3823

www.irf.com

August 1, 2013

LAYOUT RECOMMENDATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to

perform with worse than expected results.

Make the connections for the power components in

the top layer with wide, copper filled areas or

polygons. In general, it is desirable to make proper

use of power planes and polygons for power

distribution and heat dissipation.

The inductor, output capacitors and the IR3823

should be as close to each other as possible. This

helps to reduce the EMI radiated by the power

traces due to the high switching currents through

them. Place the input capacitor directly at the PVin

pin of IR3823.

The feedback part of the system should be kept

away from the inductor and other noise sources.

The critical bypass components such as capacitors

for Vin and VCC should be close to their respective

pins. It is important to place the feedback

components

including feedback

resistors

and

compensation components close to Fb and Comp

pins.

In a multilayer PCB use one layer as a power

ground plane and have a control circuit ground

(analog ground), to which all signals are referenced.

The goal is to localize the high current path to a

separate loop that does not interfere with the more

sensitive analog control function. These two grounds

must be connected together on the PC board layout

at a single point. It is recommended to place all

the compensation parts over the analog ground

plane in top layer.

The Power QFN is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 4-layers PCB. To effectively remove

heat from the device the exposed pad should be

connected to the ground plane using via holes.

Figure 41-Figure 44 illustrates the implementation of

the layout guidelines outlined above, on the

IRDC3823 4-layer demo board.

Figure 41: IRDC3823 Demo Board – Top Layer

PVin

PGnd

AGnd

Vout

Compensation parts

should be placed

as close as possible

to the Comp pin

Resistor Rt should be

placed as close as

possible to their pins

Allow enough copper &

minimum ground length

path between Input and

Output

SW node copper is

kept only at the top

layer to minimize

the switching noise

All bypass caps

should be placed

as close as possible

to their connecting pins

Single point connection

between AGND &

PGND, should be close

to the SupIRBuck and

kept away from noise

IR3823 Datasheet(PDF) 34 Page - International Rectifier

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