EP3SE110 datasheet(46/341 Pages) ALTERA

46 / 341 page

1–36

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

I/O Timing

Stratix III Device Handbook, Volume 2

Altera Corporation

I/O Default Capacitive Loading

Table 1–38 lists the default capacitive loading of various I/O standards.

MINI-LVDS_E_1R

—

100

—

120

2.325

1.02

—

1.1625

MINI-LVDS_E_3R

120

100

—

170

2.325

1.02

—

1.1625

RSDS_E_1R

—

100

—

120

2.325

1.02

—

1.1625

RSDS_E_3R

120

100

—

170

2.325

1.02

—

1.1625

Notes to Table 1–37:

(1) Hyper transport is not supported by Stratix III devices.

(2) LVPECL outputs are not supported by Stratix III devices.

(3) You can change the Quartus II timing conditions using the Advanced I/O Timing feature.

(4) V

CC is nominally 1.1 V less 50 mV (1.05 V).

(5) Terminated I/O standards require an additional 30 mV IR drop on V

CC (1.02 V).

(6) Terminated I/O standards require an additional 50 mV IR drop on V

CCIO and VCCPD.

Table 1–37. Output Timing Measurement Methodology for Output Pins (Part 3 of 3)

I/O Standard

Loading and Termination

Measurement

Point

CCIO

CCPD

L (pF)

MEAS (v)

Table 1–38. Default Loading of Various I/O Standards for Stratix III Devices (Part 1 of 2)

I/O Standard

Capacitive

Load

Unit

3.3-V LVTTL

3.3-V LVCMOS

3.0-V LVTTL

3.0-V LVCMOS

2.5-V LVTTL/LVCMOS

1.8-V LVTTL/LVCMOS

1.5-V LVTTL/LVCMOS

3.0-V PCI

3.0-V PCI-X

SSTL-2 CLASS I

SSTL-2 CLASS II

SSTL-18 CLASS I

SSTL-18 CLASS II

1.5-V HSTL CLASS I

1.5-V HSTL CLASS II

1.8-V HSTL CLASS I

1.8-V HSTL CLASS II

1.2-V HSTL

Differential SSTL-2 CLASS I

Differential SSTL-2 CLASS II

Differential SSTL-18 CLASS I

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