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EP3SE110 Datasheet(PDF) 122 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 122 Page - Altera Corporation

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1–112
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Table 1–67 lists the EP3SL110 column pins output timing parameters for differential
I/O standards.
DIFFERENTIAL
1.5-V
SSTL CLASS II
GCLK
tsu
-0.733
-0.777
-1.122 -1.220
-1.320 -1.270
-1.599
-1.220
-1.319
-1.271
-1.642
ns
t
h
0.850
0.910
1.311
1.430
1.551
1.490
1.818
1.438
1.559
1.499
1.862
ns
GCLK
PLL
t
su
1.145
1.160
1.853
2.090
2.322
2.203
2.139
2.108
2.344
2.222
2.187
ns
t
h
-0.891
-0.890
-1.449 -1.639
-1.821 -1.730
-1.658
-1.648
-1.831
-1.737
-1.702
ns
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
t
su
-0.747
-0.789
-1.131 -1.230
-1.338 -1.288
-1.617
-1.231
-1.336
-1.288
-1.659
ns
t
h
0.864
0.922
1.321
1.440
1.569
1.508
1.836
1.449
1.576
1.516
1.879
ns
GCLK
PLL
t
su
1.131
1.148
1.840
2.080
2.304
2.185
2.121
2.097
2.327
2.205
2.170
ns
th
-0.877
-0.878
-1.437 -1.629
-1.803 -1.712
-1.640
-1.637
-1.814
-1.720
-1.685
ns
DIFFERENTIAL
1.8-V
SSTL CLASS II
GCLK
t
su
-0.747
-0.789
-1.131 -1.230
-1.338 -1.288
-1.617
-1.231
-1.336
-1.288
-1.659
ns
t
h
0.864
0.922
1.321
1.440
1.569
1.508
1.836
1.449
1.576
1.516
1.879
ns
GCLK
PLL
t
su
1.131
1.148
1.840
2.080
2.304
2.185
2.121
2.097
2.327
2.205
2.170
ns
t
h
-0.877
-0.878
-1.437 -1.629
-1.803 -1.712
-1.640
-1.637
-1.814
-1.720
-1.685
ns
DIFFERENTIAL
2.5-V
SSTL CLASS I
GCLK
tsu
-0.756
-0.798
-1.145 -1.241
-1.345 -1.296
-1.623
-1.238
-1.337
-1.291
-1.661
ns
t
h
0.873
0.931
1.336
1.454
1.579
1.518
1.847
1.459
1.582
1.521
1.886
ns
GCLK
PLL
t
su
1.122
1.139
1.825
2.064
2.293
2.173
2.110
2.086
2.321
2.197
2.163
ns
t
h
-0.868
-0.869
-1.422 -1.611
-1.789 -1.698
-1.625
-1.623
-1.805
-1.711
-1.674
ns
DIFFERENTIAL
2.5-V
SSTL CLASS II
GCLK
t
su
-0.756
-0.798
-1.145 -1.241
-1.345 -1.296
-1.623
-1.238
-1.337
-1.291
-1.661
ns
t
h
0.873
0.931
1.336
1.454
1.579
1.518
1.847
1.459
1.582
1.521
1.886
ns
GCLK
PLL
t
su
1.122
1.139
1.825
2.064
2.293
2.173
2.110
2.086
2.321
2.197
2.163
ns
th
-0.868
-0.869
-1.422 -1.611
-1.789 -1.698
-1.625
-1.623
-1.805
-1.711
-1.674
ns
Table 1–66. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3)
I/O Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
LVDS_E_1R
—
GCLK
t
co
3.100
3.330
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
ns
GCLK
PLL
t
co
1.308
1.480
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
ns
LVDS_E_3R
—
GCLK
tco
3.096
3.333
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
ns
GCLK
PLL
t
co
1.304
1.483
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
ns
MINI-
LVDS_E_1R
—
GCLK
t
co
3.100
3.330
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
ns
GCLK
PLL
t
co
1.308
1.480
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
ns
MINI-
LVDS_E_3R
—
GCLK
t
co
3.096
3.333
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
ns
GCLK
PLL
tco
1.304
1.483
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
ns



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