APA150 datasheet(175/178 Pages) ACTEL

175 / 178 page

ProASICPLUS Flash Family FPGAs

v5.9

4-7

Advance v0.6

(continued)

The "Calculating Typical Power Dissipation" section was updated.

2-28

The "Absolute Maximum Ratings*" section was updated.

2-31

The "Programming, Storage, and Operating Limits" section was updated.

2-31

The "Nominal Supply Voltages’ section was updated.

1-34

The "Recommended Operating Conditions" section was updated.

2-33

The "DC Electrical Specifications (VDDP = 2.5 V ±0.2V)" section was updated.

2-34

The "DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) Applies to

Military Temperature and MIL-STD-883B Temperature Only" section was updated.

2-38

The "Synchronous Write and Read to the Same Location" section was updated.

2-61

The "Asynchronous Write and Synchronous Read to the Same Location" section was updated.

2-62

The "Asynchronous FIFO Read" section was updated.

2-67

The "Pin Description" section has been updated.

2-73

The "Recommended Design Practice for VPN/VPP" section is new.

2-74

The "100-Pin TQFP" section is new.

3-1

The "484-Pin FBGA" section is new.

3-45

Advance v0.5

The description for the VPN pin has changed.

2-74

Advance v0.4

The "Plastic Device Resources" section has been updated.

Figure 2-9 • ProASICPLUS JTAG Boundary Scan Test Logic Circuit and Figure 2-10 • TAP

Controller State Diagram have been updated.

2-11

The "Tristate Buffer Delays" section has been updated.

2-42

The "Output Buffer Delays" section has been updated.

2-44

The "Input Buffer Delays" section has been updated.

2-46

The "Global Input Buffer Delays" section has been updated.

2-48

The "456-Pin PBGA" section has been updated.

3-22

The "676-Pin FBGA" section has been updated.

3-51

Advance v0.3

The "ProASICPLUS Product Profile" section has been changed.

The "Plastic Device Resources" section has been updated.

The "ProASICPLUS I/O Power Supply Voltages" sectionhas been updated.

2-6

WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent

with the signal names found in the Macro Library Guide.

Figure 2-18 • Example SRAM Block Diagrams and Figure 2-19 • Basic FIFO Block Diagrams

have been updated.

2-22

and 2-23

The "Design Environment" section and Figure 2-23 • Tristate Buffer Delays have been

updated.

2-25

and 2-42

The table in the "Package Thermal Characteristics" section has been updated.

2-27

The "Calculating Typical Power Dissipation" section is new.

2-28

The "Programming, Storage, and Operating Limits" section is new.

2-31

The "Nominal Supply Voltages’ section has been updated.

1-34

The "DC Electrical Specifications (VDDP = 2.5 V ±0.2V)" section was updated.

2-34

The "DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) Applies to

Military Temperature and MIL-STD-883B Temperature Only" section was updated.

2-38

The "Recommended Operating Conditions" section was updated.

2-33

The "ProASICPLUS Clock Management System" section was updated.

2-10

Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram was updated.

2-11

Figure 2-10 • TAP Controller State Diagram is new.

2-9

Tables 5, 6, and 7 from Advanced v0.3 were removed.

Previous version

Changes in current version (v5.9)

Page

APA150 Datasheet(PDF) 175 Page - Actel Corporation

APA150 Datasheet(HTML) 175 Page - Actel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL