APA150 datasheet(171/178 Pages) ACTEL

171 / 178 page

ProASICPLUS Flash Family FPGAs

v5.9

4-3

v4.1

(continued)

Figure 2-27 • JTAG Operation Timing is new.

2-53

Note 1 in Table 2-52 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial was

updated.

2-55

The notes in Table 2-56 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial

were updated.

2-59

A note was added to Figure 2-45 • FIFO Reset.

2-72

A note was added to Table 2-68 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/

Industrial.

2-72

The "TRST Test Reset Input" section was updated in the "Pin Description" section.

2-73

The "624-Pin CCGA/LGA" section was updated for the APA600 and APA1000. Please review all

pin data.

3-78

v4.0

Figure 2-17 • Using the PLL for Clock Deskewing was updated.

2-16

Table 2-48 • Recommended Operating Conditions was updated.

2-52

The "1152-Pin FBGA" figure was updated.

3-69

Pin names were changed to more accurately reflect the multiple functions supported by each

pin.

v3.5

The ProASICPLUS and ProASICPLUS Military/Aerospace datasheets were combined. This

document now supports Commercial, Industrial, and Military Temperature devices.

Table 1 • ProASICPLUS Product Profile was updated.

The "Ordering Information" section was updated.

"Plastic Device Resources" table was updated.

The Long Term Jitter Peak-to-Peak Max. in the "PLL Electrical Specifications" table was updated.

2-18

The "Calculating Typical Power Dissipation" section was updated.

2-28

"Performance Retention" section

2-31

Table 2-19 • Military Temperature Grade Product Performance Retention

2-32

Table 2-21 • Recommended Operating Conditions was updated.

2-33

Table 2-22 • DC Electrical Specifications (VDDP = 2.5 V ±0.2V) was updated.

2-34

Table 2-24 • DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V) Applies

to Military Temperature and MIL-STD-883B Temperature Only was updated.

2-38

Table 2-48 • Recommended Operating Conditions was updated.

2-52

v3.4

The "Temperature Grade Offerings" table is new.

The "Speed Grade and Temperature Matrix" table is new.

The "ProASICPLUS Clock Management System" section was updated.

2-10

The "Lock Signal" section was updated.

2-13

The "PLL Electrical Specifications" table was updated.

2-18

The "User Security" section was updated.

2-20

The "Design Environment" section was updated.

2-25

Table 2-16 • Package Thermal Characteristics was updated.

2-27

The "Asynchronous FIFO Full and Empty Transitions" section was updated.

2-65

The "AVDD PLL Power Supply" section in the "Pin Description" section was updated.

2-73

v3.3

The "144-Pin TQFP" table was updated. The following pins changed:

Pin 15 = GLMX1

Pin 16 = GL1

Pin 21 = GL2

Pin 88 = GL3

Pin93 = GL4

Pin 94 = GLMX2

3-4

Previous version

Changes in current version (v5.9)

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