APA150 datasheet(172/178 Pages) ACTEL

172 / 178 page

ProASICPLUS Flash Family FPGAs

4- 4

v5.9

v3.2

The "ProASICPLUS Clock Management System" section was updated.

2-10

Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram was updated.

2-11

Table 2-7 • Clock-Conditioning Circuitry MUX Settings is new.

2-12

Figure 2-17 • Using the PLL for Clock Deskewing was updated.

2-16

The "PLL Electrical Specifications" section was updated.

2-18

Figure 2-23 • Tristate Buffer Delays was updated.

2-42

In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW.

2-28

The "Programming, Storage, and Operating Limits" section was updated.

2-31

The "Recommended Design Practice for VPN/VPP" section was updated.

2-74

v3.1

The datasheet was updated to include references to guidelines concerning the use of certain

ProASICPLUS I/O standards.

v3.0

In Table 2-2 • Array Coordinates, the Memory Rows – Bottom coordinates were changed.

2-5

Figure 2-5 • Core Cell Coordinates for the APA1000 was updated.

2-5

The VIL Minimum in the Table 2-24 • DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD

= 2.5 V ±0.2 V) Applies to Military Temperature and MIL-STD-883B Temperature Only was

changed from 0.3 to –0.3.

2-38

In the "Output Buffer Delays" section, the OB25LPLL tDHL Standard changed to 5.3.

2-44

In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7

and the –F maximum changed to 0.8.

2-51

v2.0

The Table 1 • ProASICPLUS Product Profile was updated.

The "Ordering Information" section was updated.

The "Plastic Device Resources" section was updated.

The "ProASICPLUS Architecture" section was updated.

1-2

Table 2-2 • Array Coordinates was updated.

2-5

Figure 2-5 • Core Cell Coordinates for the APA1000 is new.

2-13

Figure 2-8 • LVPECL High and Low Threshold Values is new.

2-7

The Introduction section in the "ProASICPLUS Clock Management System" section was updated.

2-10

The "Physical Implementation" section was updated.

2-10

The "Functional Description" section was updated.

2-10

Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram through Figure 2-

17 • Using the PLL for Clock Deskewing were updated.

2-11 to 2-16

The "PLL Electrical Specifications" section was updated.

2-18

Figure 2-22 • Multi-Port Memory Usage was updated.

2-24

The "Calculating Typical Power Dissipation" section was updated.

2-28

The "Nominal Supply Voltages’ section was updated.

1-34

The Table 2-24 • DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V)

Applies to Military Temperature and MIL-STD-883B Temperature Only was updated.

2-38

The "Tristate Buffer Delays" section was updated.

2-42

The "Output Buffer Delays" section was updated.

2-44

The"Input Buffer Delays" section was updated.

2-46

"Global Routing Skew" section was updated.

2-50

The"Sample Macrocell Library Listing" section was updated.

2-51

The "Pin Description" section was updated.

2-73

Previous version

Changes in current version (v5.9)

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APA150 Datasheet(PDF) 172 Page - Actel Corporation

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