CN-0279

Circuit Note

Rev. 0 | Page 2 of 5

An input signal of 1.5 dBm produces a full-scale 1.75 V p-p

differential signal at the ADC input.

The antialiasing filter is a third-order, Butterworth filter designed

with a standard filter design program. A Butterworth filter was

chosen because of its pass-band flatness. A third-order filter

yields an ac noise bandwidth ratio of 1.05 and can be designed

with the aid of several free filter programs such as Nuhertz

Technologies Filter Free, or the quite universal circuit simulator

(Qucs) free simulation.

To achieve best performance, load the ADL5565 with a net

differential load of 200 Ω. The 15 Ω series resistors isolate the

filter capacitance from the amplifier output, and the 100 Ω resistors

in parallel with the downstream impedance yield a net load

impedance of 217 Ω when added to the 30 Ω series resistance.

The 5 Ω resistors in series with the ADC inputs isolate internal

switching transients from the filter and the amplifier.

The 2.85 kΩ input impedance was determined using the down-

loadable spreadsheet on the AD9642 webpage. Simply use the

parallel track mode values at the center of the IF frequency of

interest. The spreadsheet shows both the real and imaginary values.

The third-order, Butterworth filter was designed with a source

impedance (differential) of 200 Ω, a load impedance (differential)

of 200 Ω, a center frequency of 127 MHz, and a 3 dB bandwidth

of 20 MHz. The calculated values from a standard filter design

program are shown in Figure 1. Because of the high values of

series inductance required, the 1.59 µH inductors were decreased

to 620 nH, and the 0.987 pF capacitors increased proportionally

to 2.53 pF, thereby maintaining the same resonant frequency of

127 MHz, with more realistic component values.

Figure 2. Starting Design for Third-Order, Differential Butterworth Filter with

The internal 2.5 pF capacitance of the ADC was subtracted

from the value of the second shunt capacitor to yield a value of

37.3 pF. In the circuit, this capacitor was located near the ADC

to reduce/absorb the charge kickback.

The values chosen for the final filter passive components (after

adjusting for actual circuit parasitics) are shown in Figure 1.

The measured performance of the system is summarized in

Table 1, where the 3 dB bandwidth, 18 MHz centered at 127 MHz.

The total insertion loss of the network is approximately 5.8 dB. The

frequency response is shown in Figure 3, and the SNR and SFDR

performance are shown in Figure 4.

Table 1. Measured Performance of the Circuit

Performance Specifications at −1 dBFS

(FS = 1.75V p-p), Sample Rate = 205 MSPS

Final Results

Center Frequency

127 MHz

Pass-Band Flatness (118 MHz to 136 MHz)

3 dB

SNRFS at 127 MHz

71.7 dBFS

SFDR at 127 MHz

92 dBc

H2/H3 at 127 MHz

93 dBc/92 dBc

Overall Gain at 127 MHz

5.5 dB

Input Drive at 127 MHz

0.5 dBm (−1 dBFS)

Figure 3. Pass-Band Flatness Performance vs. Frequency

Figure 4. SNR/SFDR Performance vs. Frequency, Sample Rate = 205 MSPS

39.8pF

(2.53pF)

0.987pF

(2.53pF)

0.987pF

39.5nH

39.8pF

100Ω

200Ω

(620nH)

1.59µH

(620nH)

1.59µH

100Ω

+

–

39.5nH

–40

–35

–30

–25

–20

–15

–10

–5

0

ANALOG INPUT FREQUENCY (MHz)

50

250

200

150

100

300

50

55

60

65

70

75

80

85

90

95

118

120

122

124

126

128

130

132

134

136

ANALOG INPUT FREQUENCY (MHz)

SNR (dBFS)

SFDR (dBc)