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TMS570LS0332 Datasheet(PDF) 21 Page - Texas Instruments |
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TMS570LS0332 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 101 page ![]() VCCIO VIH VIH VIL 0 Input tpw VIL TMS570LS0432 TMS570LS0332 www.ti.com SPNS186 – OCTOBER 2012 Table 3-2. Output Buffer Drive Strengths (continued) Low-level Output Current, IOL for VI=VOLmax or Signals High-level Output Current, IOH for VI=VOHmin ECLK, selectable 8mA / 2mA SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8mA for these signals. 3.8 Input Timings Figure 3-2. TTL-Level Inputs Table 3-3. Timing Requirements for Inputs(1) Parameter MIN MAX Unit tpw Input minimum pulse width tc(VCLK) + 10 (2) ns tin_slew Time for input signal to go from VIL to VIH or from VIH to VIL 1 ns (1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK) (2) The timing shown above is only valid for pin used in GIO mode. 3.9 Output Timings Table 3-4. Switching Characteristics for Output Timings versus Load Capacitance (CL) Parameter MIN MAX Unit Rise time, tr 8mA pins CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Fall time, tf CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Rise time, tr 4mA pins CL = 15 pF 5.6 ns CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Fall time, tf CL = 15 pF 5.6 ns CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 21 Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332 |
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