EP3C40 datasheet(72/274 Pages) ALTERA

72 / 274 page

5–12

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Feedback Modes

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

1 Input and output delays are fully compensated by the PLL only when you are using

the dedicated clock input pins associated with a given PLL as the clock sources. For

example, when using PLL1 in normal mode, the clock delays from the input pin to the

PLL and the PLL clock output-to-destination register are fully compensated, provided

that the clock input pin is one of the following four pins:

■

CLK0

■

CLK1

■

CLK2

■

CLK3

When driving the PLL using the GCLK network, the input and output delays may not

be fully compensated in the Quartus II software.

Source-Synchronous Mode

If the data and clock arrive at the same time at the input pins, the phase relationship

between the data and clock remains the same at the data and clock ports of any I/O

element input register.

Figure 5–8 shows an example waveform of the data and clock in this mode. Use this

mode for source-synchronous data transfers. Data and clock signals at the I/O

element experience similar buffer delays as long as the same I/O standard is used.

Source-synchronous mode compensates for delay of the clock network used,

including any difference in the delay between the following two paths:

■

Data pin to I/O element register input

■

Clock input pin to the PLL phase-frequency detector (PFD) input

1 Set the input pin to the register delay chain in the I/O element to zero in the

Quartus II software for all data pins clocked by a source-synchronous mode PLL.

Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II

software.

Figure 5–8. Phase Relationship Between Data and Clock in Source-Synchronous Mode

EP3C40 Datasheet(PDF) 72 Page - Altera Corporation