EP3C40 datasheet(81/274 Pages) ALTERA

81 / 274 page

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–21

Hardware Features

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Manual Clock Switchover

Cyclone III device family PLLs support manual switchover, in which the clkswitch

signal controls whether inclk0 or inclk1 is the input clock to the PLL. The

characteristics of a manual switchover is similar to the manual override feature in an

automatic clock switchover, in which the switchover circuit is edge-sensitive. When

the clkswitch signal goes high, the switchover sequence starts. The falling edge of the

clkswitch

signal does not cause the circuit to switch back to the previous input clock.

f For more information about PLL software support in the Quartus II software, refer to

the Phase-Locked Loop (ALTPLL) Megafunction User Guide.

Guidelines

Use the following guidelines to design with clock switchover in PLLs:

■

Clock loss detection and automatic clock switchover requires that the inclk0 and

inclk1

frequencies be within 20% of each other. Failing to meet this requirement

causes the clkbad[0] and clkbad[1] signals to function improperly.

■

When using manual clock switchover, the difference between inclk0 and inclk1

can be more than 20%. However, differences between the two clock sources

(frequency, phase, or both) can cause the PLL to lose lock. Resetting the PLL

ensures that the correct phase relationships are maintained between the input and

output clocks.

1 Both inclk0 and inclk1 must be running when the clkswitch signal goes high to

start the manual clock switchover event. Failing to meet this requirement causes the

clock switchover to malfunction.

■

Applications that require a clock switchover feature and a small frequency drift

must use a low-bandwidth PLL. When referencing input clock changes, the

low-bandwidth PLL reacts slower than a high-bandwidth PLL. When the

switchover happens, the low-bandwidth PLL propagates the stopping of the clock

to the output slower than the high-bandwidth PLL. The low-bandwidth PLL

filters out jitter on the reference clock. However, you must be aware that the

low-bandwidth PLL also increases lock time.

■

After a switchover occurs, there may be a finite resynchronization period for the

PLL to lock onto a new clock. The exact amount of time it takes for the PLL to

re-lock is dependent on the PLL configuration.

■

If the phase relationship between the input clock to the PLL and output clock from

the PLL is important in your design, assert areset for 10 ns after performing a

clock switchover. Wait for the locked signal (or gated lock) to go high before

re-enabling the output clocks from the PLL.

EP3C40 Datasheet(PDF) 81 Page - Altera Corporation

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