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SI3201-FS Datasheet(PDF) 13 Page - Silicon Laboratories |
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SI3201-FS Datasheet(HTML) 13 Page - Silicon Laboratories |
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13 / 148 page ![]() Si3210/Si3211 Rev. 1.61 13 Notes: 1. VDDD, VDDA =3.3 V. 2. VDDD, VDDA =5.25V. 3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supply regulator efficiency of 71%, the user can calculate the regulator current consumption as IBAT x VBAT/(0.71 x VDC). Table 9. Switching Characteristics (General Inputs)1 VDDA =VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL =20pF) Parameter Symbol Min Typ Max Unit Rise Time, RESET tr —— 20 ns RESET Pulse Width2 trl 100 — — ns Notes: 1. All timing (except rise and fall time) is referenced to the 50% level of the waveform. Input test levels are VIH =VD – 0.4 V, VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. Additional initialization guidelines apply; see section 1.2 ProSLIC Initialization in AN35. Table 10. Switching Characteristics (SPI) VDDA =VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL =20pF Parameter Symbol Test Conditions Min Typ Max Unit Cycle Time SCLK tc 0.062 — — µs Rise Time, SCLK tr — — 25 ns Fall Time, SCLK tf — — 25 ns Delay Time, SCLK Fall to SDO Active td1 — — 20 ns Delay Time, SCLK Fall to SDO Transition td2 — — 20 ns Delay Time, CS Rise to SDO Tri-state td3 — — 20 ns Setup Time, CS to SCLK Fall tsu1 25 — — ns Hold Time, CS to SCLK Rise th1 20 — — ns Setup Time, SDI to SCLK Rise tsu2 25 — — ns Hold Time, SDI to SCLK Rise th2 20 — — ns Delay Time between Chip Selects (Continuous SCLK) tcs 440 — — ns Delay Time between Chip Selects (Non-continuous SCLK) tcs 220 — — ns Table 8. Power Supply Characteristics (Continued) (Unless otherwise noted, VDDA, VDDD=3.13 to 5.25 V; TA=0 to 70C for F-grade, –40 to 85C for G-grade) Parameter Symbol Test Condition Typ1 Typ2 Max Unit |
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