TSB81BA3EPFP datasheet(39/57 Pages) TI

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PCLK

(a)

(c)

(b)

CTL0, CTL1

D0–D7

LREQ

LPS

tLPS_RESET

(d)

tLPS_DISABLE

TSB81BA3E

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SLLS783A – MAY 2009 – REVISED MAY 2010

When the interface is disabled, the PHY enters a low-power state if none of its ports are active.

Figure 18. Interface Disable

The sequence of events for disabling the PHY-LLC is as follows:

a. Normal operation. Interface is operating normally, with LPS active, PCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

b. LPS deasserted. The LLC deasserts the LPS signal and, within 1 s, terminates any request or interface bus

activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

c. Interface reset. After tLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus

activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

d. Interface disabled. If the LPS signal remains inactive for tLPS_DISABLE time, then the PHY terminates PCLK

activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state.

After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal

operation when LPS is reasserted by the LLC. Figure 19 shows the timing for interface initialization.

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TSB81BA3EPFP Datasheet(PDF) 39 Page - Texas Instruments