TSB81BA3EPFP datasheet(13/57 Pages) TI

13 / 57 page

TSB81BA3E

www.ti.com

SLLS783A – MAY 2009 – REVISED MAY 2010

RECOMMENDED OPERATING CONDITIONS

MIN

TYP(1)

MAX

UNIT

Source power node

3.0

3.3

3.6

3.3 VDD Supply voltage

Nonsource power node

3.0(2)

3.3

3.6

Core

Supply voltage

1.85

1.95

2.05

VDD

LREQ, CTL0, CTL1, D0-D7, LCLK

2.6

0.7 ×

LKON/DS2, PC0, PC1, PC2, PD, BMODE

VIH

High-level input voltage

VDD

0.6 ×

RESETz

VDD

LREQ, CTL0, CTL1, D0-D7, LCLK

1.2

VIL

Low-level input voltage

LKON/DS2, PC0, PC1, PC2, PD, BMODE

0.2 × VDD

RESETz

0.3 × VDD

VOD

1394b Differential output voltage

700

1394b Common-mode output

VCM

1.5

voltage

VD D = 3.3 V

Supply current in low

IDD

power/suspend(3)

VD D = 3 V

CTL0, CTL1, D0-D7, CNA, LKON/DS2, PINT, and

IOL/OH

Output current

–4

PCLK

Output current

TPBIAS outputs

–5.6

1.3

Operating ambient temperature

TSB81BA3E

°C

range

Junction temperature(4)

TSB81BA3E

105

°C

VID

1394b Differential input voltage

Cable inputs, during data reception

200

800

Cable inputs, during data reception

118

260

VID

1394a Differential input voltage

Cable inputs, during arbitration

168

265

TPB cable inputs, source power node

0.4706

2.515

1394a Common-mode input

VIC

voltage

TPB cable inputs, nonsource power node

0.4706

2.015(2)

tpu

Power-up reset time

RESETz input

2(5)

TPA, TPB cable inputs, S100 operation

±1.08

Receive input jitter

TPA, TPB cable inputs, S200 operation

±0.5

TPA, TPB cable inputs, S400 operation

±0.315

Between TPA and TPB cable inputs, S100

±0.8

operation

Between TPA and TPB cable inputs, S200

Receive input skew

±0.55

operation

Between TPA and TPB cable inputs, S400

±0.5

operation

(1)

All typical values are at VDD = 3.3 V and TA = 25°C.

(2)

For a node that does not source power, see Section 4.2.2.2 in IEEE 1394a-2000.

(3)

The low power/suspend mode assumes that the device is not receiving packets and it is toning.

(4)

The junction temperature reflects simulated conditions. The customer is responsible for verifying junction temperature.

(5)

Time after valid clock received at PHY XI input terminal.

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