AD5310

Data Sheet

Rev. B | Page 12 of 16

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 16 falling edges of SCLK, and the DAC is updated on the

16th falling edge. However, if SYNC is brought high before the

16th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset, and the write sequence is seen as

invalid. Neither an update of the DAC register contents or a

change in the operating mode occurs (see Figure 28).

POWER-ON RESET

The AD5310 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

0s, and the output voltage is 0 V. It remains there until a valid

write sequence is performed to the DAC. This is useful in

applications where it is important to know the state of the

output of the DAC while it is in the process of powering up.

POWER-DOWN MODES

The AD5310 contains four separate modes of operation. These

modes are software programmable by setting two bits (DB13

and DB12) in the control register. Table 5 shows how the state

of the bits corresponds to the mode of operation of the device.

Table 5. Modes of Operation for the AD5310

Operating Mode

DB13

DB12

Normal Operation

0

0

Power-Down Modes

1 kΩ to GND

0

1

100 kΩ to GND

1

0

Three-State

1

1

When both bits are set to 0, the part works normally with its

normal power consumption of 140 µA at 5 V. However, for the

three power-down modes, the supply current falls to 200 nA at

5 V (50 nA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage of knowing the output impedance of the part when

the part is in power-down mode. There are three options. The

output is connected internally to GND through a 1 kΩ resistor,

a 100 kΩ resistor, or it is left open-circuited (three-state). The

output stage is illustrated in Figure 26.

Figure 26. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

DAC register are unaffected when in power-down. The time to

MICROPROCESSOR INTERFACING

AD5310 to ADSP-2101 Interface

Figure 27 shows a serial interface between the AD5310 and the

ADSP-2101. The ADSP-2101 should be set up to operate in the

SPORT transmit alternate framing mode. The ADSP-2101SPORT

is programmed through the SPORT control register and should

be configured as follows: internal clock operation, active low

framing, 16-bit word length. Transmission is initiated by writing

a word to the Tx register after the SPORT has been enabled.

Figure 27. AD5310 to ADSP-2101 Interface

Figure 28. SYNC Interrupt Facility

ADSP-2101*

AD5310*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS

DT

SCLK

SYNC

DIN

SCLK