Data Sheet

AD5310

Rev. B | Page 13 of 16

AD5310 to 68HC11/68L11 Interface

Figure 29 shows a serial interface between the AD5310 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5310, while the MOSI output drives

the serial data line of the DAC. The SYNC signal is derived

from a port line (PC7). The setup conditions for correct

operation of this interface are as follows: the 68HC11/68L11

should be configured so that its CPOL bit is a 0 and its CPHA

bit is a 1. When data is being transmitted to the DAC, the SYNC

line is taken low (PC7). With this 68HC11/68L11 configuration,

data appearing on the MOSI output is valid on the falling edge

of SCK. Serial data from the 68HC11/68L11 is transmitted in

8-bit bytes with only eight falling clock edges occurring in the

transmit cycle. Data is transmitted MSB first. To load data to the

AD5310, PC7 is left low after the first eight bits are transferred,

a second serial write operation is performed to the DAC, and

PC7 is taken high at the end of this procedure.

Figure 29. AD5310 to 68HC11/68L11 Interface

AD5310 to 80C51/80L51 Interface

Figure 30 shows a serial interface between the AD5310 and the

80C51/80L51 microcontroller. The setup for the interface is as

follows: TXD of the 80C51/80L51 drives SCLK of the AD5310

while RXD drives the serial data line of the part. The SYNC

signal is again derived from a bit-programmable pin on the

port. In this case, Port Line P3.3 is used. When data is to be

transmitted to the AD5310, P3.3 is taken low. The 80C51/80L51

transmits data only in 8-bit bytes; therefore, only eight falling

clock edges occur in the transmit cycle. To load data to the

DAC, P3.3 is left low after the first eight bits are transmitted,

and a second write cycle is initiated to transmit the second byte

of data. P3.3 is taken high following the completion of this

cycle. The 80C51/ 80L51 outputs the serial data in a format that

has the LSB first. The AD5310 requires that the MSB of data be

received first. The 80C51/80L51 transmit routine should take

this into account.

Figure 30. AD5310 to 80C51/80L51 Interface

AD5310 to MICROWIRE Interface

Figure 31 shows an interface between the AD5310 and any

MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock and is clocked into the

AD5310 on the rising edge of the SK.

Figure 31. AD5310 to MICROWIRE Interface