AD9786BSVRL datasheet(42/56 Pages) AD

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AD9786

Rev. B | Page 42 of 56

Master/Slave, Modulator/DATACLK Master Modes

In applications where two or more AD9786s are used to synthe-

size several digital data paths, it might be necessary to ensure

that the digital inputs to each device are latched synchronously.

In complex data processing applications, digital modulator phase

alignment might be required between two AD9786s. To allow

data synchronization and phase alignment, only one AD9786

should be configured as a master device, providing a reference

clock for another slave-configured AD9786.

With synchronization enabled, a reference clock signal is

generated on the DATACLK pin of the master. The DATACLK

pins on the slave devices act as inputs for the reference clock

generated by the master. The DATACLK pin on the master and

all slaves must be directly connected. All master and slave devices

must have the same clock source connected to their respective

CLK+/CLK– pins.

When configured as a master, the reference clock generated can

take one of two forms. In modulator master mode, the reference

clock is a square wave with a period equal to 16 cycles of the

DAC update clock. Internal to the AD9786 is a 16-state, finite

state machine, running at the DAC update rate. This state machine

generates all internal and external synchronization clocks and

modulator phasings. The rising edge of the master reference clock

is time aligned to state zero of the internal state machine. Slave

devices use the master reference clock to synchronize data latching

and align modulator phase by aligning state zero of the local

state machine to the master.

The second master mode, DATACLK master mode, generates a

reference clock that is at the channel data rate. In this mode, the

slave devices align their internal channel data rate clock to the

master. If modulator phase alignment is needed, a concurrent

serial write to all slave devices is necessary. To achieve this, the

CSB pin on all slaves must be connected together, and a group

serial write to the MODADJ register bits must be performed.

Following a successful serial write, the modulator coefficient

alignment is updated upon the next rising edge of the internal

state machine (see Figure 81). Modulator master mode does not

need a concurrent serial write, because slaves lock to the master

phase automatically.

In a slave device, the local channel data rate clock and the

digital modulator clock are created from the internal state

machine. The local channel data rate clock is used by the slave

to latch digital input data. At high data rates, the delay inherent

in the signal path from master to slave can cause the slave to lag

the master when acquiring synchronization. To accommodate

for this, an integer number of the DAC update clock cycles can

be programmed into the slave device as an offset. The value in

DATAADJ allows the local channel data rate clock in the slave

device to advance by up to eight cycles of the DAC clock, or to

be delayed by up to seven cycles (see Figure 82).

The digital modulator coefficients are updated at the DAC clock

rate and decoded in sequential order from the state machine

according to Figure 83. The MODADJ bits can be used to align

a different coefficient to the finite state machine’s zero state, as

shown in Figure 84.

DAC

CLOCK

STATE

MACHINE

STATE MACHINE

CHANNEL DATA

CYCLE CLOCK

RATE CLOCK

MODULATOR

COEFFICIENT

MODADJ

000

–1

010

–1

010

–1

010

–1

2345

6789

23456

789

Figure 81. Synchronous Serial Modulator Phase Alignment

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