AD9786BSVRL datasheet(44/56 Pages) AD

44 / 56 page

AD9786

Rev. B | Page 44 of 56

OPERATING THE AD9786 REV. F EVALUATION BOARD

This section provides information to power up the board and

verify correct operation; a description of more advanced modes

of operation has been omitted.

POWER SUPPLIES

The AD9786 Rev. F evaluation board has five power supply

connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD,

CLKVDD, and DVDD, whereas the AD9786 has seven power

supply domains. To reconcile the power supply domains on the

chip with the power supply connectors on the evaluation board,

use Table 38.

Additionally, the DRVDD power supply on the AD9786 is used

to supply power for the digital input bus. DRVDD should be

run from 3.3 V. On the evaluation board, DRVDD is jumper-

selectable by JP1, which is just to the left of the chip on the

evaluation board. With the jumper set to the 3.3 V position, the

DRVDD chip receives its power from VDD3IN.

PECL CLOCK DRIVER

The AD9786 system clock is driven from an external source via

Connector S1. The AD9786 evaluation board includes an

ON Semiconductor® MC100EPT22 PECL clock driver. In the

factory, the evaluation board is set to use this PECL driver as a

single-ended-to-differential clock receiver. The PECL driver can

be set to run from 2.5 V from the CLKVDD power connector

or 3.3 V from the VDD3IN power connector. This setting is

done via Jumper JP2, situated next to the CLKVDD power

connector, and by setting Input Bias Resistor R23 and Input

Bias Resistor R4 on the evaluation board. The factory default is

for the PECL driver to be powered from CLKVDD at 2.5 V

(R23 = 90.9 Ω, R4 = 115 Ω). To operate the PECL driver with

a 3.3 V supply, R23 must be replaced with a 115 Ω resistor; R4

must be replaced with a 90.9 Ω resistor; and the position of JP2

must be changed. The schematic of the PECL driver section of

the evaluation board is shown in Figure 85. A low jitter sine

wave should be used as the clock source. Care must be taken to

ensure that the clock amplitude does not exceed the power

supply rails for the PECL driver.

COND;5

CLKVDDS;8

C32

0.1

μF

R23

115

90.9

ACLKX

CLKVDDS

MC100EPT22

CLK+

CLK–

Figure 85. PECL Driver on AD9786 Rev. F Evaluation Board

Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board

Evaluation Board Label/PS Domain on Chip

Nominal Power

Supply Voltage (V)

Description

DVDD

2.5

SPI port

CLKVDD

2.5

Clock circuitry

ACVDD/ADVDD

2.5

Analog circuitry containing clock and digital interface circuitry

AVDD2

3.3

Switching analog circuitry

AVDD1

3.3

Analog output circuitry

AD9786BSVRL Datasheet(PDF) 44 Page - Analog Devices

AD9786BSVRL Datasheet(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL