RL78_13 datasheet(21/31 Pages) RENESAS

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RL78/G10

CHAPTER 2 ELECTRICAL SPECIFICATIONS

R01DS0207EJ0100 Rev.1.00

Apr 15, 2013

Page 21 of 28

(4) Simplified I

2C mode

(TA =

−40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

SCLr clock frequency

fSCL

2.0 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

400

Note 1

kHz

Hold time when SCLr = "L"

tLOW

2.0 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1150

Hold time when SCLr = "H"

tHIGH

2.0 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1150

Data setup time (reception)

tSU: DAT

2.0 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1/fMCK +

145

Note 2

Data hold time (transmission)

tHD: DAT

2.0 V

≤ VDD ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

355

Notes 1.

The value must also be equal to or less than fMCK/4.

Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".

Caution Select the N-ch open drain output (VDD tolerance) mode for the SDAr pin by using the port output mode

Remarks 1. Rb [

Ω]: Communication line (SDAr) pull-up resistance, Cb [F]: Communication line (SCLr, SDAr) load

capacitance

2. r: IIC number (r = 00)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).

m: Unit number, n: Channel number (mn = 00))

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