AD5040 datasheet(18/24 Pages) AD

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AD5512A/AD5542A

Rev. A | Page 18 of 24

APPLICATIONS INFORMATION

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5512A/AD5542A is via

a serial bus that uses standard protocol that is compatible with

DSP processors and microcontrollers. The communications

channel requires a 3- or 4-wire interface consisting of a clock

signal, a data signal, and a synchronization signal. The

AD5512A/AD5542A require a 16-bit data-word with data

valid on the rising edge of SCLK. The DAC update can be

done automatically when all the data is clocked in, or it can

be done under the control of the LDAC.

AD5512A/AD5542A TO ADSP-BF531 INTERFACE

The SPI interface of the AD5512A/AD5542A is designed to be

easily connected to industry-standard DSPs and micro-

controllers. Figure 33 shows how the AD5512A/AD5542A

can be connected to the Analog Devices, Inc., Blackfin® DSP.

The Blackfin has an integrated SPI port that can be connected

directly to the SPI pins of the AD5512A/AD5542A.

AD5512A/

AD5542A

SCLK

DIN

LDAC

SPISELx

SCK

MOSI

PF9

ADSP-BF531

Figure 33. AD5512A/AD5542A to ADSP-BF531 Interface

AD5512A/AD5542A TO SPORT INTERFACE

The Analog Devices ADSP-BF527 has one SPORT serial port.

Figure 34 shows how one SPORT interface can be used to

control the AD5512A/AD5542A.

AD5512A/

AD5542A

SCLK

DIN

LDAC

SPORT_TFS

SPORT_TSCK

SPORT_DTO

GPIO0

ADSP-BF527

Figure 34. AD5512A/AD5542A to ADSP-BF527 Interface

AD5512A/AD5542A TO 68HC11/68L11 INTERFACE

Figure 35 shows a serial interface between the AD5512A/

AD5542A and the 68HC11/68L11 microcontroller. SCK of

the 68HC11/68L11 drives the SCLK of the DAC, and the

MOSI output drives the serial data line serial DIN. The CS

signal is driven from one of the port lines. The 68HC11/68L11 is

configured for master mode: MSTR = 1, CPOL = 0, and CPHA =

0. Data appearing on the MOSI output is valid on the rising

edge of SCK.

LDAC

DIN

SCLK

PC6

PC7

MOSI

SCK

AD5512A/

AD5542A*

68HC11/

68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 35. AD5512A/AD5542A to 68HC11/68L11 Interface

AD5512A/AD5542A TO ADSP-2101 INTERFACE

Figure 36 shows a serial interface between the AD5512A/

AD5542A and the ADSP-2101. The ADSP-2101 should be

set to operate in the SPORT transmit alternate framing mode.

The ADSP-2101 is programmed through the SPORT control

operation, active low framing, 16-bit word length. Transmission

is initiated by writing a word to the Tx register after the SPORT

has been enabled. As the data is clocked out on each rising edge

of the serial clock, an inverter is required between the DSP and

the DAC, because the AD5512A/AD5542A clock data in on the

falling edge of the SCLK.

LDAC

DIN

SCLK

TFS

SCLK

AD5512A/

AD5542A*

ADSP-2101

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 36. AD5512A/AD5542A to ADSP-2101 Interface

AD5512A/AD5542A TO MICROWIRE INTERFACE

Figure 37 shows an interface between the AD5512A/AD5542A

and any MICROWIRE-compatible device. Serial data is shifted

out on the falling edge of the serial clock and into the AD5512A/

AD5542A on the rising edge of the serial clock. No glue logic

is required because the DAC clocks data into the input shift

DIN

SCLK

AD5512A/

AD5542A*

MICROWIRE*

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 37. AD5512A/AD5542A to MICROWIRE Interface

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