AD5379ABC datasheet(7/29 Pages) AD

7 / 29 page

AD5379

Rev. B | Page 6 of 28

TIMING CHARACTERISTICS

SERIAL INTERFACE

VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = 5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V;

VBIAS = 5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter1, 2, 3

Limit at TMIN, TMAX

Unit

Description

ns min

SCLK cycle time.

ns min

SCLK high time.

ns min

SCLK low time.

ns min

SYNC falling edge to SCLK falling edge setup time.

t54

ns min

24th SCLK falling edge to SYNC falling edge.

t64

ns min

Minimum SYNC low time.

ns min

Minimum SYNC high time.

ns min

Data setup time.

4.5

ns min

Data hold time.

t104, 5

ns max

24th SCLK falling edge to BUSY falling edge.

t11

330

ns max

BUSY pulse width low (single-channel update). See

Table 10

t124

ns min

24th SCLK falling edge to LDAC falling edge.

t13

ns min

LDAC pulse width low.

t14

150

ns typ

BUSY rising edge to DAC output response time.

t15

ns min

BUSY rising edge to LDAC falling edge.

t16

100

ns min

LDAC falling edge to DAC output response time.

t17

20/30

μs typ/max

DAC output settling time.

t18

ns min

CLR pulse width low.

t19

350

ns max

CLR/RESET pulse activation time.

t206, 7

ns max

SCLK rising edge to sdo valid.

t217

ns min

SCLK falling edge to SYNC rising edge.

t227

ns min

SYNC rising edge to SCLK rising edge.

t237

ns min

SYNC rising edge to LDAC falling edge.

t245

ns min

SYNC rising edge to BUSY falling edge.

t25

ns min

RESET pulse width low.

t26

120

μs max

RESET time indicated by BUSY low.

1 Guaranteed by design and characterization, not production tested.

2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC), and timed from a voltage level of 1.2 V.

3 See Figure 4 and Figure 5.

4 Standalone mode only.

5 This is measured with the load circuit shown in Figure 2.

6 This is measured with the load circuit shown in Figure 3.

7 Daisy-chain mode only.

OUTPUT

VCC

VOL

50pF

2.2k

Figure 2. Load Circuit for BUSY Timing Diagram

VOH(min) + VOL(max)

200

μA

200

μA

IOL

IOH

50pF

OUTPUT

Figure 3. Load Circuit for SDO Timing Diagram

(Serial Interface, Daisy-Chain Mode)

AD5379ABC Datasheet(PDF) 7 Page - Analog Devices

AD5379ABC Datasheet(HTML) 7 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL