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AM3703CUS Datasheet(PDF) 247 Page - Texas Instruments

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Part # AM3703CUS
Description  Sitara ARM Microprocessors
PDF  280 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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AM3703CUS Datasheet(HTML) 247 Page - Texas Instruments

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AM3715, AM3703
www.ti.com
SPRS616F
– JUNE 2010 – REVISED AUGUST 2011
Table 6-111. MMC1 Interface Switching Characteristics
—SD Identification Modes(4) (7) (continued)
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
tR(data)
Rise time, output data
10
10
ns
tF(data)
Fall time, output data
10
10
ns
SD5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to mmc1_cmd
6.3
2492.7
6.3
2492.7
ns
transition
MMC1 Interface (3.0-V IO)
tR(clk)
Rise time, output clock
10
10
ns
tF(clk)
Fall time, output clock
10
10
ns
tR(data)
Rise time, output data
10
10
ns
tF(data)
Fall time, output data
10
10
ns
SD5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to mmc1_cmd
6.3
2492.7
6.3
2492.7
ns
transition
(1) Related with the output clock maximum and minimum frequencies programmable in mmc module.
(2) PO = output clock period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) Corresponding figures showing timing parameters are common with other interface modes. (See SD, HS SD modes).
(5) The X parameter is defined as follows:
CLKD
X
1 or Even
0.5
Odd
(trunk[CLKD/2]+1)/CLKD
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
(6) The Y parameter is defined as follows:
CLKD
Y
1 or Even
0.5
Odd
(trunk[CLKD/2])/CLKD
All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
(7) See Section 4.3.4, Processor Clocks.
6.6.8.1.2 MMC1 Interface
—High-Speed SD Mode
Table 6-113 and Table 6-114 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-65 and Figure 6-66).
Table 6-112. MMC1 Interface Timing Conditions
—High-Speed SD Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
3
ns
tF
Input signal fall time
3
ns
Output Condition
CLOAD
Output load capacitance(1)
40
pF
(1) Buffer strength configuration: SPEEDCTRL = 1.
Copyright
© 2010–2011, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
247
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Product Folder Link(s): AM3715 AM3703



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