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AM3703CUS Datasheet(PDF) 251 Page - Texas Instruments |
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AM3703CUS Datasheet(HTML) 251 Page - Texas Instruments |
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251 / 280 page  AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 Table 6-116. MMC1 Interface Timing Requirements —Standard SD Mode(1) (2) (4) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising 18.1 36.7 ns clock edge SD7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](3) valid before mmc1_clk 3.3 21.9 ns rising clock edge SD8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](3) valid after mmc1_clk 18.1 36.7 ns rising clock edge (1) Timing parameters are referred to output clock specified in Table 6-117. (2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-117. (3) In mmc1_dat[n:0], n is equal to 3. (4) See Section 4.3.4, Processor Clocks. Table 6-117. MMC1 Interface Switching Characteristics —Standard SD Mode(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX Standard SD Mode SD1 tc(clk) Frequency(1), output clock period 24 12 MHz SD2 tW(clkH) Typical pulse duration, output clock high X(4)*PO(2) X(4)*PO(2) ns SD2 tW(clkL) Typical pulse duration, output clock low Y(5)*PO(2) Y(5)*PO(2) ns tdc(clk) Duty cycle error, output clock 2083.33 4166.67 ps tJ(clk) Jitter standard deviation(3), output clock 200 200 ps MMC1 Interface (1.8-V) tR(clk) Rise time, output clock 10 10 ns tF(clk) Fall time, output clock 10 10 ns tR(data) Rise time, output data 10 10 ns tF(data) Fall time, output data 10 10 ns SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 6.13 35.53 6.3 77.03 ns transition SD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to 6.13 35.53 6.3 77.03 ns mmc1_dat[n:0](6) transition MMC1 Interface (3.0-V) tR(clk) Rise time, output clock 10 10 ns tF(clk) Fall time, output clock 10 10 ns tR(data) Rise time, output data 10 10 ns tF(data) Fall time, output data 10 10 ns SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 6.13 35.53 6.3 77.03 ns transition SD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to 6.13 35.53 6.3 77.03 ns mmc1_dat[n:0](6) transition (1) Related with the output clock maximum and minimum frequencies programmable in MMC module. (2) PO = output clock period in ns (3) The jitter probability density can be approximated by a Gaussian function. (4) The X parameter is defined as follows: CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 251 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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