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AM3703CUS Datasheet(PDF) 249 Page - Texas Instruments |
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AM3703CUS Datasheet(HTML) 249 Page - Texas Instruments |
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249 / 280 page ![]() AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 Table 6-114. MMC1 Interface Switching Characteristics —High-Speed SD Mode(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX High-Speed SD Mode HSSD1 tc(clk) Frequency(1), output clock period 48 24 MHz HSSD2 tW(clkH) Typical pulse duration, output clock high X(4)*PO(2) X(4)*PO(2) ns HSSD2 tW(clkL) Typical pulse duration, output clock low Y(5)*PO(2) Y(5)*PO(2) ns tdc(clk) Duty cycle error, output clock 1041.67 2083.33 ps tJ(clk) Jitter standard deviation(3), output clock 200 200 ps MMC1 Interface (1.8-V IO) tR(clk) Rise time, output clock 3 3 ns tF(clk) Fall time, output clock 3 3 ns tR(data) Rise time, output data 3 3 ns tF(data) Fall time, output data 3 3 ns HSSD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 3.72 14.11 4.13 34.53 ns transition HSSD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to 3.72 14.11 4.13 34.53 ns mmc1_dat[n:0](6) transition MMC1 Interface (3.0-V IO) tR(clk) Rise time, output clock 3 3 ns tF(clk) Fall time, output clock 3 3 ns tR(data) Rise time, output data 3 3 ns tF(data) Fall time, output data 3 3 ns HSSD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 3.72 14.11 4.13 34.53 ns transition HSSD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to 3.72 14.11 4.13 34.53 ns mmc1_dat[n:0](6) transition (1) Related with the output clock maximum and minimum frequencies programmable in MMC module. (2) PO = output clock period in ns (3) The jitter probability density can be approximated by a Gaussian function. (4) The X parameter is defined as follows: CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (5) The Y parameter is defined as follows: CLKD Y 1 or Even 0.5 Odd (trunk[CLKD/2])/CLKD All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (6) In mmc1_dat[n:0], n is equal to 3. (7) See Section 4.3.4, Processor Clocks. Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 249 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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