AM3703CUS datasheet(265/280 Pages) TI

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SWPS038-107

sdti_clk

sdti_txd[3:0]

Header

Ad[7:4]

Ad[3:0]

Da[15:12]

Da[11:8]

Da[7:4]

Da[3:0]

SD1

SD2

SD3

AM3715, AM3703

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SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

6.6.9.2

System Debug Trace Interface (SDTI)

The System Debug Trace Interface (SDTI) module provides real-time software tracing functionality to the

device. The trace interface has four trace data pins and a trace clock pin.

This interface is a dual-edge interface:

•

The data are available on rising and falling edge of sdti_clk.

•

But can be also configured in single-edge mode where data are available on the falling edge of

sdti_clk.

Serial interface operates in clock stop regime: serial clock is not free-running; when there is no trace data,

there is no trace clock.

6.6.9.2.1 SDTI

—Dual-Edge Mode

Table 6-139 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-80).

Table 6-138. SDTI Timing Conditions

—Dual-Edge Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Output Condition

CLOAD

Output load capacitance(1)

(1) Buffer strength configuration: LB0 = 1.

Table 6-139. SDTI Switching Characteristics

—Dual-Edge Mode(2)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

SD1

1 / tc(clk)

Frequency, output clock sdti_clk

34.5

MHz

SD2

tw(clk)

Pulse duration, output clock sdti_clk high or low

0.5P(1)

–

0.5P(1) +

0.5P(1)

–

0.5P(1) +

1.2

SD3

td(clk-txd)

Delay time, output clock sdti_clk

Multiplexing mode on

2.3

10.9

2.3

10.9

transition to output data

etk pins

sdti_txd[3:0] transition

Multiplexing mode on

2.3

13.9

2.3

13.9

jtag_emu pins

(1) P = sdti_clk clock period in ns

(2) See Section 4.3.4, Processor Clocks.

Figure 6-80. SDTI

—Dual-Edge Mode

Timing Requirements and Switching Characteristics

265

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