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AM3703CUS Datasheet(PDF) 267 Page - Texas Instruments |
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AM3703CUS Datasheet(HTML) 267 Page - Texas Instruments |
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267 / 280 page  AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 Table 6-143. JTAG Timing Requirements —Free-Running Clock Mode(5) (6) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX JT4 1 / tc(tck) Frequency(1), input clock jtag_tck 50 50 MHz JT5 tw(tckL) Pulse duration, input clock jtag_tck low 0.5P(2) 0.5P(2) ns JT6 tw(tckH) Pulse duration, input clock jtag_tck high 0.5P(2) 0.5P(2) ns tdc(tck) Duty cycle error, input clock jtag_tck –1250 1250 –1667 1667 ps tJ(tck) Cycle jitter(3), input clock jtag_tck –1250 1250 –1667 1667 ps JT7 tsu(tdiV-rtckH) Setup time, input data jtag_tdi valid before output 1.6 1.6 ns clock jtag_rtck high JT8 th(tdiV-rtckH) Hold time, input data jtag_tdi valid after output clock 0.7 1.0 ns jtag_rtck high JT9 tsu(tmsV-rtckH) Setup time, input mode select jtag_tms_tmsc valid 1.6 1.6 ns before output clock jtag_rtck high JT10 th(tmsV-rtckH) Hold time, input mode select jtag_tms_tmsc valid after 0.7 1.0 ns output clock jtag_rtck high JT12 tsu(emuxV-rtckH) Setup time, input emulation jtag_emux(4) valid before 14.4 19.6 ns output clock jtag_rtck high JT13 th(emuxV-rtckH) Hold time, input emulation jtag_emux(4) valid after 2.0 2.7 ns output clock jtag_rtck high (1) Related with the input maximum frequency supported by the JTAG module. (2) P = input clock jtag _tck period in ns (3) Maximum cycle jitter supported by input clock jtag _tck. (4) In jtag_emux, x is equal to 0 or 1. (5) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (6) See Section 4.3.4, Processor Clocks. Table 6-144. JTAG Switching Characteristics —Free-Running Clock Mode(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX JT1 1 / tc(rtck) Frequency(1), output clock jtag_rtck 50 50 MHz JT2 tw(rtckL) Pulse duration, output clock jtag_rtck low 0.5P(2) 0.5P(2) ns JT3 tw(rtckH) Pulse duration, output clock jtag_rtck high 0.5P(2) 0.5P(2) ns tdc(rtck) Duty cycle error, output clock jtag_rtck –1250 1250 –1667 1667 ps tJ(rtck) Jitter standard deviation(3), output clock jtag_rtck 33.3 33.3 ps tR(rtck) Rise time, output clock jtag_rtck 0 0 ns tF(rtck) Fall time, output clock jtag_rtck 0 0 ns JT11 td(rtckL-tdoV) Delay time, output clock jtag_rtck low to output data –5.8 5.8 –7.9 7.9 ns jtag_tdo valid tR(tdo) Rise time, output data jtag_tdo 0 0 ns tF(tdo) Fall time, output data jtag_tdo 0 0 ns JT14 td(rtckH-emuxV) Delay time, output clock jtag_rtck high to output 2.7 15.1 2.7 20.4 ns emulation ,jtag_emux(4) valid (1) Related with the jtag_rtck maximum frequency. (2) P = output clock jtag _rtck period in ns (3) The jitter probability density can be approximated by a Gaussian function. (4) In jtag_emux, x is equal to 0 or 1. (5) See Section 4.3.4, Processor Clocks. Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 267 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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