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EP3C80 Datasheet(PDF) 116 Page - Altera Corporation |
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EP3C80 Datasheet(HTML) 116 Page - Altera Corporation |
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116 / 274 page  6–18 Chapter 6: I/O Features in the Cyclone III Device Family I/O Banks Cyclone III Device Handbook July 2012 Altera Corporation Volume 1 1 When VREF pins are used as regular I/Os, they have higher pin capacitance than regular user I/O pins. This has an impact on the timing if the pins are used as inputs and outputs. f For more information about VREF pin capacitance, refer to the pin capacitance section in the Cyclone III Device Data Sheet and Cyclone III LS Device Data Sheet chapters. f For more information about how to identify VREF groups, refer to the Cyclone III Device Family Pin-Out files or the Quartus II Pin Planner tool. Table 6–6 lists the number of VREF pins in each I/O bank for Cyclone III and Cyclone III LS devices. Table 6–6. Number of VREF Pins Per I/O Banks for Cyclone III and Cyclone III LS Devices (Part 1 of 2) Family Device Package Pin Count I/O Banks 12 345 678 EP3C5 EQFP 144 11 111 111 MBGA 164 11 111 111 FBGA 256 11 111 111 EP3C10 EQFP 144 11 111 111 MBGA 164 11 111 111 FBGA 256 11 111 111 EP3C16 EQFP 144 22 222 222 MBGA 164 22 222 222 PQFP 240 22 222 222 FBGA 256 22 222 222 FBGA 484 22 222 222 EP3C25 EQFP 144 11 111 111 PQFP 240 11 111 111 FBGA 256 11 111 111 FBGA 324 11 111 111 EP3C40 PQFP 240 44 444 444 FBGA 324 44 444 444 FBGA 484 44 444 444 FBGA 780 44 444 444 EP3C55 FBGA 484 22 222 222 FBGA 780 22 222 222 EP3C80 FBGA 484 33 333 333 FBGA 780 33 333 333 EP3C120 FBGA 484 33 333 333 FBGA 780 33 333 333 |
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