EP3C80 datasheet(115/274 Pages) ALTERA

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Chapter 6: I/O Features in the Cyclone III Device Family

6–17

I/O Banks

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Table 6–5 lists the I/O standards supported when a pin is used as a regular I/O pin in

the I/O banks of the Cyclone III device family.

Each I/O bank of the Cyclone III device family has a VREF bus to accommodate

voltage-referenced I/O standards. Each VREF pin is the reference source for its VREF

group. If you use a VREF group for voltage-referenced I/O standards, connect the VREF

pin for that group to the appropriate voltage level. If you do not use all the VREF

groups in the I/O bank for voltage referenced I/O standards, you can use the VREF pin

in the unused voltage referenced groups as regular I/O pins. For example, if you have

SSTL-2 Class I

input pins in I/O bank 1 and they are all placed in the VREFB1N0

group, VREFB1N0 must be powered with 1.25 V, and the remaining VREFB1N[1:3] pins

(if available) are used as I/O pins. If multiple VREF groups are used in the same I/O

bank, the VREF pins must all be powered by the same voltage level because the VREF

pins are shorted together within the same I/O bank.

Table 6–5. Cyclone III Device Family I/O Standards Support

I/O Standard

I/O Banks

123

4567

3.3-V LVTTL/LVCMOS,

3.0-V LVTTL/LVCMOS,

2.5-V LVTTL/LVCMOS,

1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS,

1.2V LVCMOS,

3.0-V PCI/PCI-X

vvv

vvvv

SSTL-18 Class I/II,

SSTL-2 Class I/II,

HSTL-18 Class I/II,

HSTL-15 Class I/II,

HSTL-12 Class I

vvv

vvvv

HSTL-12 Class II

——

Differential SSTL-2,

Differential SSTL-18,

Differential HSTL-18,

Differential HSTL-15,

Differential HSTL-12

(1)

PPDS (2), (3)

(3)

LVDS (2)

vvv

vvvv

BLVDS

vvv

vvvv

RSDS and mini-LVDS (2)

(3)

Differential LVPECL

(4)

Notes to Table 6–5:

(1) These differential I/O standards are supported only for clock inputs and dedicated PLL_OUT outputs.

(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks only. Differential outputs in

column I/O banks require an external resistors network.

(3) This I/O standard is supported for outputs only.

(4) This I/O standard is supported for clock inputs only.

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