EP3C80 datasheet(145/274 Pages) ALTERA

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Chapter 8: External Memory Interfaces in the Cyclone III Device Family

8–3

Cyclone III Device Family Memory Interfaces Pin Support

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

1 Cyclone III device family does not support differential strobe pins, which is an

optional feature in the DDR2 SDRAM device.

f When you use the Altera Memory Controller MegaCore®, the PHY is instantiated for

you. For more information about the memory interface data path, refer to the External

Memory Interfaces page.

1 ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the

implementation of the read-data path in different memory interfaces. The

auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock

phases and frequencies across process, voltage, and temperature (PVT) variations.

You can save on the global clock resources in Cyclone III device family through the

ALTMEMPHY megafunction because you are not required to route the DQS signals on

the global clock buses (because DQS is ignored for read capture). Resynchronization

issues do not arise because no transfer occurs from the memory domain clock (DQS) to

the system domain for capturing data DQ.

All I/O banks in Cyclone III device family can support DQ and DQS signals with DQ-bus

modes of ×8, ×9, ×16, ×18, ×32, and ×36. DDR2 and DDR SDRAM interfaces use ×8

mode DQS group regardless of the interface width. For wider interface, you can use

multiple ×8 DQ groups to achieve the desired width requirement.

In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)

drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or four

parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support the

QDR II memory interface. CQ# is the inverted read-clock signal which is connected to

the complementary data strobe (DQS or CQ#) pin. You can use any unused DQ pins as

regular user I/O pins if they are not used as memory interface signals.

Table 8–1 lists the number of DQS or DQ groups supported on each side of the

Cyclone III device only.

Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 4)

Device

Package

Side

Number

×8

Groups

Number

×9

Groups

Number

×16

Groups

Number

×18

Groups

Number

×32

Groups

Number

×36

Groups

EP3C5

144-pin EQFP (1)

Left

0000

—

Right

0000

—

Top (2)

1000

—

Bottom (3), (4)

1000

—

164-pin MBGA (1)

Left

0000

—

Right

0000

—

Top (2)

1000

—

Bottom (3), (4)

1000

—

256-pin FineLine

BGA/256-pin

Ultra FineLine

BGA (1)

Left (4), (5)

1100

—

Right (4), (6)

1100

—

Top

2211

—

Bottom

2211

—

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