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EP3C80 Datasheet(PDF) 148 Page - Altera Corporation |
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EP3C80 Datasheet(HTML) 148 Page - Altera Corporation |
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148 / 274 page ![]() 8–6 Chapter 8: External Memory Interfaces in the Cyclone III Device Family Cyclone III Device Family Memory Interfaces Pin Support Cyclone III Device Handbook July 2012 Altera Corporation Volume 1 EP3C55 484-pin FineLine BGA/484-pin Ultra FineLine BGA Left 42221 1 Right 42221 1 Top 42221 1 Bottom 42221 1 780-pin FineLine BGA Left 42221 1 Right 42221 1 Top 62221 1 Bottom 62221 1 EP3C80 484-pin FineLine BGA/484-pin Ultra FineLine BGA Left 42221 1 Right 42221 1 Top 42221 1 Bottom 42221 1 780-pin FineLine BGA Left 42221 1 Right 42221 1 Top 62221 1 Bottom 62221 1 EP3C120 484-pin FineLine BGA Left 42221 1 Right 42221 1 Top 42221 1 Bottom 42221 1 780-pin FineLine BGA Left 42221 1 Right 42221 1 Top 62221 1 Bottom 62221 1 Notes to Table 8–1: (1) This device package does not support ×32 or ×36 mode. (2) For the top side of the device, RUP, RDN, PLLCLKOUT3n, and PLLCLKOUT3p pins are shared with the DQ or DM pins to gain ×8 DQ group. You cannot use these groups if you are using the RUP and RDN pins for on-chip termination (OCT) calibration or if you are using PLLCLKOUT3n and PLLCLKOUT3p. (3) There is no DM pin support for these groups. (4) The RUP and RDN pins are shared with the DQ pins. You cannot use these groups if you are using the RUP and RDN pins for OCT calibration. (5) The ×8 DQ group can be formed in Bank 2. (6) The ×8 DQ group can be formed in Bank 5. (7) There is no DM and BWS# pins support for these groups. (8) The RUP pin is shared with the DQ pin to gain ×9 or ×18 DQ group. You cannot use these groups if you are using the RUP and RDN pins for OCT calibration. Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 4 of 4) Device Package Side Number ×8 Groups Number ×9 Groups Number ×16 Groups Number ×18 Groups Number ×32 Groups Number ×36 Groups |
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